PRELIMINARY
CY27EE16ZE
1 PLL In-system Programmable Clock
Generator with Individual 16K EEPROM
Features
• 18 bits of EEPROM
16 kbits independent scratch
2 kbits dedicated to clocking functions
Benefits
Higher level of integration and reduced component count by
combining EEPROM and PLL
Independent EEPROM may be used for scratch memory, or to
store up to eight clock configurations
• Integrated, phase-locked loop with programmable P
High-performance PLL enables control of output frequencies
and Q counters, output dividers, and optional analog
that are customizable to support a wide range of applications
VCXO, digital VCXO, spread spectrum for EMI reduction
• In system programmable through I
2
C Serial Program-
ming Interface (SPI). Both the SRAM and non volatile
EEPROM memory bits are programmable with the 3.3V
supply
• Low-jitter, high-accuracy outputs
• VCXO with analog adjust
Familiar industry standard eases programming effort and en-
ables update of data stored in 16K EEPROM scratchpad and
2K EEPROM clock control block while CY27EE16ZE is in-
stalled in system
Meets critical timing requirements in complex system designs
Write Protect (WP pin) can be programmed to serve as an
analog control voltage for a VCXO.The VCXO function is still
available with a DCXO, or digitally controlled (through SPI)
crystal oscillator if the pin is functioning as WP
Meets industry-standard voltage platforms
Industry standard packaging saves on board space
• 3.3V Operation (optional 2.5V outputs)
• 20-lead Exposed Pad, EP-TSSOP
Part Number
CY27EE16ZE
Outputs
6
Input Frequency Range
Output Frequency Range
1 – 167 MHz (Driven Clock Input) {Commercial} 80 kHz – 200 MHz (3.3V) {Commercial}
1 –150 MHz (Driven Clock Input) {Industrial}
80 kHz –167 MHz (3.3V) {Industrial}
8 – 30 MHz (Crystal Reference) {Comm. or Ind.} 80 kHz –167 MHz (2.5V) {Commercial}
80 kHz – 150 MHz (2.5V) {Industrial}
Logic Block Diagram
XIN
XOUT
OSC
Q
Φ
VCO
P
OUTPUT
DIVIDERS
Output
Crosspoint
Switch
Array
CLOCK1
CLOCK2
CLOCK3
CLOCK4
PLL
CLOCK5
VCX/WP
PDM/OE
Clock
Configuration
CLOCK6
8x2k EEPROM
Memory Array
Pin Configurations
CY27EE16ZE
[I
2
C- SPI:]
SCL
SDAT
20-pin EP-TSSOP
XIN 1
VDD 2
VDD
VSS
VDDL
VSSL
AVDD AVSS
20 XOUT
19 VDD
18 CLOCK5
17 VCXO/WP
16 VSS
15 CLOCK4
14 VDDL
13 SCL
12 CLOCK3
11 VDDL
CLOCK6 3
AVDD 4
SDAT 5
AVSS 6
VSSL 7
CLOCK1 8
CLOCK2 9
OE/PDM 10
Cypress Semiconductor Corporation
Document #: 38-07440 Rev. *A
•
3901 North First Street
•
San Jose
•
CA 95134 • 408-943-2600
Revised December 14, 2002
PRELIMINARY
Table 1. Pin Description
Name
Pin Number Description
XIN
1
Reference crystal input
VDD
CLOCK6
AVDD
SDAT
AVSS
VSSL
CLOCK1
CLOCK2
OE/PDM
VDDL
CLOCK3
SCL
CLOCK4
VSS
VCXO/WP
CLOCK5
XOUT
[1]
2, 19
3
4
5
6
7
8
9
10
11,14
12
13
15
16
17
18
20
3.3V voltage supply
Clock output 6
3.3V analog voltage supply
Data input for serial programming
Analog ground
Output ground
Clock output 1
Clock output 2
Output enable or power-down mode enable
Output voltage supply
Clock output 3
Clock signal input for serial programming
Clock output 4
Ground
Analog control input for VCXO or write protect (user configurable)
Clock output 5
Reference crystal output
CY27EE16ZE
Note:
1. Float XOUT if XIN is externally driven
Functional Description
The CY27EE16ZE integrates a 16-kbit EEPROM scratchpad
and a clock generator that features Cypress’s programmable
clock core. An industry standard I
2
C serial programming
interface (SPI) is used to program the scratchpad and clock
core.
16-kbit EEPROM
The 16-kbit EEPROM scratchpad is organized in 8 blocks x
256 words x 8 bits. Each of the eight 2-kbit EEPROM
scratchpad blocks, a 2-kbit clock configuration EEPROM
block, and a 2-kbit volatile clock configuration SRAM block,
have their own 7-bit device address. The device address is
combined with a Read/Write bit as the LSB and is sent after
each start bit.
Clock Features
The programmable clock core is configured with the following
features:
•
Crystal Oscillator:
Programmable drive and load, support
for external references up to 166 MHz. See section "Refer-
ence Frequency (REF)", page 5
•
VCXO:
Analog or digital control
•
Inputs and I/Os:
Programmable input muxes drive write
protect (WP), analog VCXO control, output enable (OE),
and power down mode (PDM) functions
•
PLL:
Programmable P, Q, offset, and loop filter parameters
Outputs:
Six outputs and two programmable linear dividers.
The output swing of CLOCK1 through CLOCK4 is set by VDDL
(2.5V or 3.3V). The output swing of CLOCK5 and CLOCK6 is
set by VDD (3.3V).
Clock configuration is stored in a dedicated 2-kbit block of
nonvolatile EEPROM and a 2-kbit block of volatile SRAM. The
SPI is used to write new configuration data to the on-chip
programmable registers that are defined within the clock
configuration memory blocks. Other, custom configurations,
that include custom VCXO, Spread Spectrum for EMI
reduction, Fractional N and frequency select pins (FS) are
programmable; contact factory for details.
Write Protect (WP) - Active HIGH
The default clock configuration of the CY27EE16ZE has pin
17 configured as WP. When a logical HIGH level input is as-
serted on this pin, the write protect feature (WP) will inhibit
writing to the EEPROM. This protects EEPROM bits from be-
ing changed, while allowing full read access to EEPROM. Writ-
ing to SRAM is allowed with WP enabled. When this pin is held
at a logical LOW level, WP is disabled and data can be written
to EEPROM.
Analog Adjust for Voltage Controlled Crystal Oscillator
(VCXO)
Pin 17 can be programmed, with the SPI, to function as the
analog control for the VCXO. Then, pin 17 provides ±150 ppm
adjustment of the crystal oscillator frequency (in order to use
the VCXO, the crystal must have a minimum of ±150 ppm pull
range and meet the pullable crystal specifications as shown in
Table 15
on page 13). The crystal oscillator frequency is pulled
lower by at least 150 ppm when 0V is applied to VCXO, pulled
higher by at least 150 ppm when V
DD
is applied to VCXO. The
oscillator frequency will have a linear dependence on the
voltage level applied to pin 17, VCXO, within a range from 0V
to V
DD
. See section "Device Addressing", page 10 for more
information.
Document #: 38-07440 Rev. *A
Page 2 of 18
PRELIMINARY
Output Enable (OE) - Active HIGH
The default clock configuration has pin 10 programmed as an
Output Enable (OE). This pin enables the divider bank clock
outputs when HIGH, and disables divider bank clock outputs
when LOW.
Power-down Mode (PDM) - Active LOW
The Power-down Mode (PDM) function is available when pin
10 of the CY27EE16ZE is configured as PDM. When the PDM
signal pulled LOW, all clock components are shut down and
the part enters a low-power state. To configure pin 10 of the
CY27EE16ZE as PDM, see "Power-down Mode (PDM) and
Output Enable (OE) Registers for Pin 10", page 7.
Serial Programming Interface (SPI)
The SPI uses industry-standard signaling in both standard and
fast modes to program the 8 x 2 kbit EPPROM blocks of
scratchpad, the 2-kbit EEPROM dedicated to clock configu-
ration, and the 2-kbit SRAM block. See sections beginning
with "Using the Serial Programming Interface (SPI)", page 3
for more information.
CY27EE16ZE
This default clock configuration is typically customized to meet
the needs of a specific application. It provides a clock signal
upon power-on, to facilitate in-system programming. Alterna-
tively, the CY27EE16ZE may be programmed with a different
clock configuration prior to placement of the CY27EE16ZE in
systems. While you can develop your own subroutine to
program any or all of the individual registers described in the
following pages, it may be easier to use CyClocksRT™ to
produce the required register setting file.
Using the Serial Programming Interface (SPI)
The CY27EE16ZE provides an industry-standard serial pro-
gramming interface for volatile and nonvolatile, in-system pro-
gramming of unique frequencies and options. Serial program-
ming and reprogramming allows for quick design changes and
product enhancements, eliminates inventory of old design
parts, and simplifies manufacturing.
The CY27EE16ZE is a group of ten slave devices with ad-
dresses as shown in
Figure 1.
The serial programming inter-
face address of the CY27EE16ZE clock configuration 2-kbit
EEPROM block is 69H. The serial programming interface ad-
dress of the CY27EE16ZE clock configuration 2-kbit SRAM
block is 68H. Should there be a conflict with any other devices
in your system, all device addresses can also be changed us-
ing CyberClocks. Registers in the clock configuration 2-kbit
SRAM memory block are written, when the user wants to up-
date the clock configuration for on-the-fly changes
.
Registers
in the clock configuration EEPROM block are written, if the
user wants to update the clock configuration so that it is saved
and used again after power-up or reset.
All programmable registers in the CY27EE16ZE are ad-
dressed with 8 bits and contain 8 bits of data.
Table 2
lists the
specific register definitions and their allowable values. See
section "Serial Programming Interface Timing", page 13, for a
detailed description.
Default Start-up Condition for CY27EE16ZE
The default (programmed) condition of the 8 x 256 bit EE-
PROM blocks (scratchpad) in the device as shipped from the
factory, are blank and unprogrammed. In this condition, all bits
are set to 0.
The default clock configuration is:
• the crystal oscillator circuit is active.
• CLOCK1 outputs REF frequency.
• All other outputs are tri-stated.
• WP control on pin 17
• OE control on pin 10
1st
EE block
256 x 8 bits
Address:
1000000
clock config.
EE block
256 x 8 bits
Address:
1101000
2nd
EE block
256 x 8 bits
Address:
1000001
clock config.
SRAM
256 x 8 bits
Address:
1101001
3rd
EE block
256 x 8 bits
Address:
1000010
4th
EE block
256 x 8 bits
Address:
1000011
5th
EE block
256 x 8 bits
Address:
1000100
6th
EE block
256 x 8 bits
Address:
1000101
7th
EE block
256 x 8 bits
Address:
1000110
8th
EE block
256 x 8 bits
Address:
1000111
Figure 1. Device Addresses for EEPROM Scratchpad and Clock Configuration Blocks
Table 2. Summary Table - CY27EE16ZE Programmable Registers
Register Description
09H
OCH
10H
CLKOE control
DIV1SRC mux and
DIV1N divider
Input Pin Control
Registers
Write Protect
Registers
D7
0
DIV1SR
C
OESrc
D6
CLOCK6
D5
CLOCK5
D4
0
D3
CLOCK4
D2
CLOCK3
D1
CLOCK2
D0
CLOCK1
DIV1N(6) DIV1N(5) DIV1N(4) DIV1N(3) DIV1N(2) DIV1N(1) DIV1N(0)
OE0Pad
Sel[1]
OE0Pad
Sel[0]
OE1Pad
Sel[1]
MemWP
OE1Pad
Sel[0]
WPSrc
PDME-
nable
WPPad-
Sel[2]
PDM-
Pad-
Sel[1]
WPPad-
Sel[1]
PDM-
Pad-
Sel[0]
WPPad-
Sel[0]
11H
Document #: 38-07440 Rev. *A
Page 3 of 18
PRELIMINARY
Table 2. Summary Table - CY27EE16ZE Programmable Registers
(continued)
Register Description
12H
Input crystal
oscillator drive
control
Input load capacitor
control
ADC Register
Charge Pump and
PB counter
PO counter, Q
counter
Crosspoint switch
matrix control
D7
D6
D5
D4
XDRV(1)
D3
XDRV(0)
D2
0
CY27EE16ZE
D1
0
D0
0
FTAAd-
FTAAd- XCapSrc
drSrc(1)
drSrc(0) default=1
default=0 default=0
Cap-
Load(7)
ADCEn-
able
1
PB(7)
PO
CLKSRC
2 for
CLOCK1
CLKSRC
0 for
CLOCK3
CLKSRC
1 for
CLOCK5
Cap-
Load(6)
AD-
CBypCnt
1
PB(6)
Q(6)
CLKSRC
1 for
CLOCK1
CLKSRC
2 for
CLOCK4
CLKSRC
0 for
CLOCK5
Cap-
Load(5)
ADC-
Cnt[2]
0
PB(5)
Q(5)
CLKSRC
0 for
CLOCK1
CLKSRC
1 for
CLOCK4
CLKSRC
2 for
CLOCK6
13H
14H
40H
41H
42H
44H
Cap-
Load(4)
ADC-
Cnt[1]
Pump(2)
PB(4)
Q(4)
CLKSRC
2 for
CLOCK2
CLKSRC
0 for
CLOCK4
CLKSRC
1 for
CLOCK6
Cap-
Load(3)
ADC-
Cnt[0]
Pump(1)
PB(3)
Q(3)
CLKSRC
1 for
CLOCK2
1
Cap-
Load(2)
ADC-
Filt[1]
Pump(0)
PB(2)
Q(2)
CLKSRC
0 for
CLOCK2
1
Cap-
Load(1)
ADC-
Filt[0]
PB(9)
PB(1)
Q(1)
CLKSRC
2 for
CLOCK3
1
Cap-
Load(0)
0
PB(8)
PB(0)
Q(0)
CLKSRC
1 for
CLOCK3
CLKSRC
2 for
CLOCK5
1
45H
46H
CLKSRC
0 for
CLOCK6
1
1
47H
DIV2SRC mux and
DIV2N divider
DIV2SR
C
DIV2N(6) DIV2N(5) DIV2N(4) DIV2N(3) DIV2N(2) DIV2N(1) DIV2N(0)
The basic PLL block diagram is shown in
Figure 2.
Each of the
six clock outputs on the CY27EE16ZE has a total of seven
output options available to it. There are six post divider options
available: /2 (two of these), /3, /4, /DIV1N and /DIV2N. DIV1N
and DIV2N are independently calculated and are applied to
individual output groups. The post divider options can be ap-
plied to the calculated VCO frequency ((REF*P)/Q) or to the
reference frequency directly.
In addition to the six post divider output options, the seventh
option bypasses the PLL and passes the reference frequency
directly to the crosspoint switch matrix.
CY27EE16ZE Frequency Calculation and
Register Definitions
The CY27EE16ZE is an extremely flexible clock generator
with four basic variables that can be used to determine the final
output frequency. They are the input reference frequency
(REF), the internally calculated P and Q dividers, and the post
divider, which can be a fixed or calculated value. There are
three basic formulas for determining the final output frequency
of a CY27EE16ZE-based design. Any one of these three for-
mulas may be used:
CLK = ((REF * P)/Q)/Post Divider
CLK = REF/Post Divider
CLK = REF
Document #: 38-07440 Rev. *A
Page 4 of 18
PRELIMINARY
DIV1N [OCH]
DIV1SRC [OCH]
1
CY27EE16ZE
CLKSRC
Crosspoint
Switch Matrix
Q
total
/DIV1N
[44H]
[44H]
CLOCK1
CLOCK2
CLOCK3
CLOCK4
DIV1CLK
REF
(
Q+2)
[42H]
PFD
VCO
P
total
0
/2
[44H,45H]
(2(PB+4)+PO)
[40H], [41H], [42H]
1
/
3
Divider Bank 1
Divider Bank 2
[45H]
/
4
/
2
/DIV2N
DIV2CLK
0
[45H,46h]
[46H]
CLOCK5
CLOCK6
DIV2SRC [47H]
DIV2N [47H]
CLKOE [09H]
Figure 2. Basic Block Diagram of CY27EE16ZE PLL
Reference Frequency (REF)
The reference frequency can be a crystal or a driven frequen-
cy. For crystals, the frequency range must be between 8 MHz
and 30 MHz. For a driven frequency, the frequency range must
be between 1 MHz and 167 MHz (Commercial Temp.) or
150 MHz (Industrial Temp.).
Using a Crystal as the Reference Input
The input crystal oscillator of the CY27EE16ZE is an important
feature because of the flexibility it allows the user in selecting
a crystal as a reference frequency source. The input oscillator
has programmable gain, allowing for maximum compatibility
with a reference crystal, regardless of manufacturer, process,
performance and quality.
Programmable Crystal Input Oscillator Gain Settings
The Input crystal oscillator gain (XDRV) is controlled by 2 bits
in register 12H, and are set according to
Table 3.
The param-
eters controlling the gain are the crystal frequency, the internal
crystal parasitic resistance (ESR, available from the manufac-
turer), and the CapLoad setting during crystal start-up.
Bits 3 and 4 of register 12H control the input crystal oscillator
gain setting. Bit 4 is the MSB of the setting, and bit 3 is the
LSB. The setting is programmed according to
Table 3.
All other bits in the register are reserved and should be pro-
grammed LOW. See
Table 4
for bit locations and values.
Table 3. Programmable Crystal Input Oscillator Gain Settings
Calculated CapLoad Value
Crystal ESR
8 – 15 MHz
Crystal
Input
Frequency
15 – 20 MHz
20 – 25 MHz
25 – 30 MHz
00
01
01
10
00H – 20H
30Ω
60Ω
01
10
10
10
01
01
10
10
20H – 30H
30Ω
60Ω
10
10
10
11
01
10
10
11
30H – 40H
30Ω
60Ω
10
10
11
N/A
Table 4. Register Map for Input Crystal Oscillator Gain Setting
Address
12H
D7
FTAAd-
drSrc(1)
default=0
D6
FTAAd-
drSrc(0)
default=0
D5
XCapSrc
default=1
D4
XDRV(1)
D3
XDRV(0)
D2
0
D1
0
D0
0
Document #: 38-07440 Rev. *A
Page 5 of 18
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