74S65FCQM datasheet, PDF - EEWORLD Datasheet

EEWORLDEEWORLD

Datasheet

Datasheet> All Categories > logic> logic> 74S65FCQM

Preview

74S65FCQM: DescriptionAND-OR-Invert Gate, TTL, CDFP14,; Categorylogic logic; File Size40KB，1 Pages; ManufacturerFairchild; Websitehttp://www.fairchildsemi.com/

Download Datasheet Parametric Compare View All

74S65FCQM Overview

AND-OR-Invert Gate, TTL, CDFP14,

74S65FCQM Parametric

Parameter Name	Attribute value
Is it lead-free?	Contains lead
Is it Rohs certified?	incompatible
Maker	Fairchild
package instruction	DFP, FL14,.3
Reach Compliance Code	compliant
JESD-30 code	R-XDFP-F14
JESD-609 code	e0
Logic integrated circuit type	AND-OR-INVERT GATE
MaximumI(ol)	0.02 A
Humidity sensitivity level	2A
Number of terminals	14
Maximum operating temperature	70 °C
Minimum operating temperature
Output characteristics	OPEN-COLLECTOR
Package body material	CERAMIC
encapsulated code	DFP
Encapsulate equivalent code	FL14,.3
Package shape	RECTANGULAR
Package form	FLATPACK
Peak Reflow Temperature (Celsius)	250
Prop。Delay @ Nom-Sup	8.5 ns
Certification status	Not Qualified
Schmitt trigger	NO
surface mount	YES
technology	TTL
Temperature level	COMMERCIAL
Terminal surface	Tin/Lead (Sn/Pb)
Terminal form	FLAT
Terminal pitch	1.27 mm
Terminal location	DUAL
Maximum time at peak reflow temperature	30

Preview

Download Datasheet

View All

74S65FCQM Related Products

	74S65FCQM	74S65DCQM	74S65DCQR	74S65DCQC	74S65FCQR	74S65FCQC	74S65PCQR	74S65PCQM
Description	AND-OR-Invert Gate, TTL, CDFP14,	AND-OR-Invert Gate, TTL, CDIP14,	AND-OR-Invert Gate, TTL, CDIP14,	AND-OR-Invert Gate, TTL, CDIP14,	AND-OR-Invert Gate, TTL, CDFP14,	AND-OR-Invert Gate, TTL, CDIP14,	AND-OR-Invert Gate, TTL, PDIP14,	AND-OR-Invert Gate, TTL, PDIP14,
Is it lead-free?	Contains lead	Contains lead	Contains lead	Contains lead	Contains lead	Contains lead	Contains lead	Contains lead
Is it Rohs certified?	incompatible	incompatible	incompatible	incompatible	incompatible	incompatible	incompatible	incompatible
Maker	Fairchild	Fairchild	Fairchild	Fairchild	Fairchild	Fairchild	Fairchild	Fairchild
package instruction	DFP, FL14,.3	DIP, DIP14,.3	DIP, DIP14,.3	DIP, DIP14,.3	DFP, FL14,.3	DIP, DIP14,.3	DIP, DIP14,.3	DIP, DIP14,.3
Reach Compliance Code	compliant	compliant	compliant	compliant	compliant	compliant	compliant	compliant
JESD-30 code	R-XDFP-F14	R-XDIP-T14	R-XDIP-T14	R-XDIP-T14	R-XDFP-F14	R-XDIP-T14	R-PDIP-T14	R-PDIP-T14
JESD-609 code	e0	e0	e0	e0	e0	e0	e0	e0
Logic integrated circuit type	AND-OR-INVERT GATE	AND-OR-INVERT GATE	AND-OR-INVERT GATE	AND-OR-INVERT GATE	AND-OR-INVERT GATE	AND-OR-INVERT GATE	AND-OR-INVERT GATE	AND-OR-INVERT GATE
MaximumI(ol)	0.02 A	0.02 A	0.02 A	0.02 A	0.02 A	0.02 A	0.02 A	0.02 A
Humidity sensitivity level	2A	2A	2A	2A	2A	2A	2A	2A
Number of terminals	14	14	14	14	14	14	14	14
Maximum operating temperature	70 °C	70 °C	70 °C	70 °C	70 °C	70 °C	70 °C	70 °C
Output characteristics	OPEN-COLLECTOR	OPEN-COLLECTOR	OPEN-COLLECTOR	OPEN-COLLECTOR	OPEN-COLLECTOR	OPEN-COLLECTOR	OPEN-COLLECTOR	OPEN-COLLECTOR
Package body material	CERAMIC	CERAMIC	CERAMIC	CERAMIC	CERAMIC	CERAMIC	PLASTIC/EPOXY	PLASTIC/EPOXY
encapsulated code	DFP	DIP	DIP	DIP	DFP	DIP	DIP	DIP
Encapsulate equivalent code	FL14,.3	DIP14,.3	DIP14,.3	DIP14,.3	FL14,.3	DIP14,.3	DIP14,.3	DIP14,.3
Package shape	RECTANGULAR	RECTANGULAR	RECTANGULAR	RECTANGULAR	RECTANGULAR	RECTANGULAR	RECTANGULAR	RECTANGULAR
Package form	FLATPACK	IN-LINE	IN-LINE	IN-LINE	FLATPACK	IN-LINE	IN-LINE	IN-LINE
Peak Reflow Temperature (Celsius)	250	250	250	250	250	250	250	250
Prop。Delay @ Nom-Sup	8.5 ns	8.5 ns	8.5 ns	8.5 ns	8.5 ns	8.5 ns	8.5 ns	8.5 ns
Schmitt trigger	NO	NO	NO	NO	NO	NO	NO	NO
surface mount	YES	NO	NO	NO	YES	NO	NO	NO
technology	TTL	TTL	TTL	TTL	TTL	TTL	TTL	TTL
Temperature level	COMMERCIAL	COMMERCIAL	COMMERCIAL	COMMERCIAL	COMMERCIAL	COMMERCIAL	COMMERCIAL	COMMERCIAL
Terminal surface	Tin/Lead (Sn/Pb)	Tin/Lead (Sn/Pb)	Tin/Lead (Sn/Pb)	Tin/Lead (Sn/Pb)	Tin/Lead (Sn/Pb)	Tin/Lead (Sn/Pb)	Tin/Lead (Sn/Pb)	Tin/Lead (Sn/Pb)
Terminal form	FLAT	THROUGH-HOLE	THROUGH-HOLE	THROUGH-HOLE	FLAT	THROUGH-HOLE	THROUGH-HOLE	THROUGH-HOLE
Terminal pitch	1.27 mm	2.54 mm	2.54 mm	2.54 mm	1.27 mm	2.54 mm	2.54 mm	2.54 mm
Terminal location	DUAL	DUAL	DUAL	DUAL	DUAL	DUAL	DUAL	DUAL
Maximum time at peak reflow temperature	30	30	30	30	30	30	30	30
Certification status	Not Qualified	Not Qualified	-	Not Qualified	-	Not Qualified	-	Not Qualified

Recommended Resources

Voice changing signal generator circuit

STK459 power amplifier circuit diagram

Control end manual or electrical signal control diagram (b)

Hybrid power amplifier final circuit b

Contact combustion type CO detection circuit

Resistor-frequency converter circuit for temperature adjustment

Shortcut: A0 A1 A2 A3 A4 A5 A6 A7 A8 A9 AA AB AC AD AE AF AG AH AI AJ AK AL AM AN AO AP AQ AR AS AT AU AV AW AX AY AZ B0 B1 B2 B3 B4 B5 B6 B7 B8 B9 BA BB BC BD BE BF BG BH BI BJ BK BL BM BN BO BP BQ BR BS BT BU BV BW BX BY BZ C0 C1 C2 C3 C4 C5 C6 C7 C8 C9 CA CB CC CD CE CF CG CH CI CJ CK CL CM CN CO CP CQ CR CS CT CU CV CW CX CY CZ D0 D1 D2 D3 D4 D5 D6 D7 D8 D9 DA DB DC DD DE DF DG DH DI DJ DK DL DM DN DO DP DQ DR DS DT DU DV DW DX DZ

Popular Components