PEEL22LV10AZT-25 datasheet, PDF

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PEEL22LV10AZT-25: DescriptionEE PLD, 25ns, PAL-Type, CMOS, PDSO24, 0.170 INCH, TSSOP-24; CategoryProgrammable logic devices Programmable logic; File Size135KB，10 Pages; ManufacturerIntegrated Circuit Systems（IDT ）

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PEEL22LV10AZT-25 Overview

EE PLD, 25ns, PAL-Type, CMOS, PDSO24, 0.170 INCH, TSSOP-24

PEEL22LV10AZT-25 Parametric

Parameter Name	Attribute value
Is it Rohs certified?	incompatible
Maker	Integrated Circuit Systems（IDT ）
Parts packaging code	TSSOP
package instruction	TSSOP, TSSOP24,.25
Contacts	24
Reach Compliance Code	unknown
Other features	10 MACROCELLS; 1 EXTERNAL CLOCK; SHARED INPUT/CLOCK
Architecture	PAL-TYPE
maximum clock frequency	25 MHz
JESD-30 code	R-PDSO-G24
JESD-609 code	e0
length	7.8 mm
Dedicated input times	11
Number of I/O lines	10
Number of entries	22
Output times	10
Number of product terms	133
Number of terminals	24
Maximum operating temperature	70 °C
Minimum operating temperature
organize	11 DEDICATED INPUTS, 10 I/O
Output function	MACROCELL
Package body material	PLASTIC/EPOXY
encapsulated code	TSSOP
Encapsulate equivalent code	TSSOP24,.25
Package shape	RECTANGULAR
Package form	SMALL OUTLINE, THIN PROFILE, SHRINK PITCH
power supply	3/3.3 V
Programmable logic type	EE PLD
propagation delay	25 ns
Certification status	Not Qualified
Maximum seat height	1.1 mm
Maximum supply voltage	3.6 V
Minimum supply voltage	2.7 V
Nominal supply voltage	3 V
surface mount	YES
technology	CMOS
Temperature level	COMMERCIAL
Terminal surface	Tin/Lead (Sn/Pb)
Terminal form	GULL WING
Terminal pitch	0.65 mm
Terminal location	DUAL
width	4.4 mm

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Commercial/Industrial

PEEL™ 22LV10AZ-25 / I-35

CMOS Programmable Electrically Erasable Logic Device

Features

•

Low Voltage, Ultra Low Power Operation

- Vcc = 2.7 to 3.6 V

- Icc = 5 µA (typical) at standby

- Icc = 1.5 mA (typical) at 1 MHz

- Meets JEDEC LV Interface Spec (JESD8-B)

- 5 Volt tolerant inputs and I/O’s

CMOS Electrically Erasable Technology

- Superior factory testing

- Reprogrammable in plastic package

- Reduces retrofit and development costs

Application Versatility

- Replaces random logic

- Super set of standard PLDs

- Pin and JEDEC compatible with 22V10

- Ideal for battery powered systems

- Replaces expensive oscillators

•

Architectural Flexibility

- Enhanced architecture fits in more logic

- 133 product terms x 44 input AND array

- 12 inputs and 10 I/O pins

- 12 possible macrocell configurations

- Asynchronous clear, synchronous preset

- Independent output enables

- Programmable clock; pin 1 or p-term

- Programmable clock polarity

- 24-Pin DIP/SOIC/TSSOP and 28 Pin PLCC

- Schmitt triggers on clock and data inputs

Schmitt Trigger Inputs

- Eliminates external Schmitt trigger devices

- Ideal for encoder designs

•

General Description

The PEEL22LV10AZ is a Programmable Electrically

Erasable Logic (PEEL) SPLD (Simple Programmable

Logic Device) that operates over the supply voltage

range of 2.7V-3.6V and features ultra-low, automatic

"zero" power-down operation. The PEEL22LV10AZ is

logically and functionally similar to ICT's 5V

PEEL22CV10A and PEEL22CV10AZ. The "zero power"

(25

µA

max. I

) power-down mode makes the

PEEL22LV10AZ ideal for a broad range of battery-

powered portable equipment applications, from hand-

held

meters

PCMCIA

modems.

EE-

reprogrammability provides both the convenience of

product fast reprogramming for product development

and quick personalization in manufacturing, including

Engineering Change Orders.

Figure 1 - Pin Configuration

I/CLK

G ND

VCC

I/O

I/CLK

G ND

VCC

I/O

The differences between the PEEL22LV10AZ and

PEEL22CV10A include the addition of programmable

clock polarity, p-term clock, and Schmitt trigger input

buffers on all inputs, including the clock. Schmitt trigger

inputs allow direct input of slow signals such as

biomedical and sine waves or clocks. Like the

PEEL22CV10A, the PEEL22LV10AZ is a pin and

JEDEC compatible, logical superset of the industry

standard

PAL22V10

SPLD

Figure

The

PEEL22LV10AZ provides additional architectural

features that allow more logic to be incorporated into

the design. The PEEL22LV10AZ architecture allows it

to replace over twenty standard 24-pin DIP, SOIC,

TSSOP

and

PLCC

packages.

Figure 2 - Block Diagram

CLK MUX (O ptiona l)

4 3 2 1 28 27 26

12 13 14 15 16 17 18

I/CLK

VCC

I/O

DIP

TSSOP

I/CLK

PEEL

T M

"AND"

ARRAY

MACRO

CEL L

I/O

133 Terms

44 Inp uts

I/O

G ND

I/O

I/CLK

G ND

VCC

I/O

SP = SYNCHRONO US PRESET

AC = ASYNCHRONO US CLEAR

O E = O UTPUT ENABLE

PLCC

SOIC

04-02-037D

PEEL22LV10AZT-25 Related Products

	PEEL22LV10AZT-25	PEEL22LV10AZSI-35	PEEL22LV10AZJ-25	PEEL22LV10AZS-25	PEEL22LV10AZP-25
Description	EE PLD, 25ns, PAL-Type, CMOS, PDSO24, 0.170 INCH, TSSOP-24	EE PLD, 35ns, CMOS, PDSO24, 0.300 INCH, SOIC-24	EE PLD, 25ns, PAL-Type, CMOS, PQCC28, PLASTIC, LCC-28	EE PLD, 25ns, PAL-Type, CMOS, PDSO24, 0.300 INCH, SOIC-24	EE PLD, 25ns, PAL-Type, CMOS, PDIP24, 0.300 INCH, PLASTIC, DIP-24
Parts packaging code	TSSOP	SOIC	QLCC	SOIC	DIP
package instruction	TSSOP, TSSOP24,.25	SOP,	QCCJ, LDCC28,.5SQ	SOP, SOP24,.4	DIP, DIP24,.3
Contacts	24	24	28	24	24
Reach Compliance Code	unknown	unknown	unknown	unknown	unknown
maximum clock frequency	25 MHz	17.9 MHz	25 MHz	25 MHz	25 MHz
JESD-30 code	R-PDSO-G24	R-PDSO-G24	S-PQCC-J28	R-PDSO-G24	R-PDIP-T24
length	7.8 mm	15.4 mm	11.5062 mm	15.4 mm	31.75 mm
Dedicated input times	11	11	11	11	11
Number of I/O lines	10	10	10	10	10
Number of terminals	24	24	28	24	24
Maximum operating temperature	70 °C	85 °C	70 °C	70 °C	70 °C
organize	11 DEDICATED INPUTS, 10 I/O	11 DEDICATED INPUTS, 10 I/O	11 DEDICATED INPUTS, 10 I/O	11 DEDICATED INPUTS, 10 I/O	11 DEDICATED INPUTS, 10 I/O
Output function	MACROCELL	MACROCELL	MACROCELL	MACROCELL	MACROCELL
Package body material	PLASTIC/EPOXY	PLASTIC/EPOXY	PLASTIC/EPOXY	PLASTIC/EPOXY	PLASTIC/EPOXY
encapsulated code	TSSOP	SOP	QCCJ	SOP	DIP
Package shape	RECTANGULAR	RECTANGULAR	SQUARE	RECTANGULAR	RECTANGULAR
Package form	SMALL OUTLINE, THIN PROFILE, SHRINK PITCH	SMALL OUTLINE	CHIP CARRIER	SMALL OUTLINE	IN-LINE
Programmable logic type	EE PLD	EE PLD	EE PLD	EE PLD	EE PLD
propagation delay	25 ns	35 ns	25 ns	25 ns	25 ns
Certification status	Not Qualified	Not Qualified	Not Qualified	Not Qualified	Not Qualified
Maximum supply voltage	3.6 V	3.6 V	3.6 V	3.6 V	3.6 V
Minimum supply voltage	2.7 V	2.7 V	2.7 V	2.7 V	2.7 V
Nominal supply voltage	3 V	3.3 V	3 V	3 V	3 V
surface mount	YES	YES	YES	YES	NO
technology	CMOS	CMOS	CMOS	CMOS	CMOS
Temperature level	COMMERCIAL	INDUSTRIAL	COMMERCIAL	COMMERCIAL	COMMERCIAL
Terminal form	GULL WING	GULL WING	J BEND	GULL WING	THROUGH-HOLE
Terminal pitch	0.65 mm	1.27 mm	1.27 mm	1.27 mm	2.54 mm
Terminal location	DUAL	DUAL	QUAD	DUAL	DUAL
width	4.4 mm	7.5 mm	11.5062 mm	7.5 mm	7.62 mm
Is it Rohs certified?	incompatible	-	incompatible	incompatible	incompatible
Maker	Integrated Circuit Systems（IDT ）	-	Integrated Circuit Systems（IDT ）	Integrated Circuit Systems（IDT ）	Integrated Circuit Systems（IDT ）
Other features	10 MACROCELLS; 1 EXTERNAL CLOCK; SHARED INPUT/CLOCK	-	10 MACROCELLS; 1 EXTERNAL CLOCK; SHARED INPUT/CLOCK	10 MACROCELLS; 1 EXTERNAL CLOCK; SHARED INPUT/CLOCK	10 MACROCELLS; 1 EXTERNAL CLOCK; SHARED INPUT/CLOCK
Architecture	PAL-TYPE	-	PAL-TYPE	PAL-TYPE	PAL-TYPE
JESD-609 code	e0	-	e0	e0	e0
Number of entries	22	-	22	22	22
Output times	10	-	10	10	10
Number of product terms	133	-	133	133	133
Encapsulate equivalent code	TSSOP24,.25	-	LDCC28,.5SQ	SOP24,.4	DIP24,.3
power supply	3/3.3 V	-	3/3.3 V	3/3.3 V	3/3.3 V
Maximum seat height	1.1 mm	2.65 mm	4.369 mm	2.64 mm	-
Terminal surface	Tin/Lead (Sn/Pb)	-	Tin/Lead (Sn/Pb)	Tin/Lead (Sn/Pb)	Tin/Lead (Sn/Pb)

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