PA7024P-1 datasheet, PDF - EEWORLD Datasheet

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PA7024P-1: DescriptionEE PLD, 20ns, CMOS, PDIP24, 0.300 INCH, PLASTIC, DIP-24; CategoryProgrammable logic devices Programmable logic; File Size798KB，9 Pages; ManufacturerAMI Semiconductor

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PA7024P-1 Overview

EE PLD, 20ns, CMOS, PDIP24, 0.300 INCH, PLASTIC, DIP-24

PA7024P-1 Parametric

Parameter Name	Attribute value
Is it Rohs certified?	incompatible
Maker	AMI Semiconductor
package instruction	0.300 INCH, PLASTIC, DIP-24
Reach Compliance Code	unknown
Other features	SHARED INPUT/CLOCK
maximum clock frequency	41.6 MHz
JESD-30 code	R-PDIP-T24
JESD-609 code	e0
length	31.75 mm
Dedicated input times
Number of I/O lines	20
Number of entries	22
Output times	20
Number of terminals	24
Maximum operating temperature	70 °C
Minimum operating temperature
organize	0 DEDICATED INPUTS, 20 I/O
Output function	MACROCELL
Package body material	PLASTIC/EPOXY
encapsulated code	DIP
Encapsulate equivalent code	DIP24,.3
Package shape	RECTANGULAR
Package form	IN-LINE
Peak Reflow Temperature (Celsius)	NOT SPECIFIED
power supply	5 V
Programmable logic type	EE PLD
propagation delay	20 ns
Certification status	Not Qualified
Maximum seat height	4.699 mm
Maximum supply voltage	5.25 V
Minimum supply voltage	4.75 V
Nominal supply voltage	5 V
surface mount	NO
technology	CMOS
Temperature level	COMMERCIAL
Terminal surface	Tin/Lead (Sn/Pb)
Terminal form	THROUGH-HOLE
Terminal pitch	2.54 mm
Terminal location	DUAL
Maximum time at peak reflow temperature	NOT SPECIFIED
width	7.62 mm

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PA7024P-1 Related Products

	PA7024P-1	PA7024J-2	PA7024P-2	PA7024J-1	PA7024C-2	PA7024C-1
Description	EE PLD, 20ns, CMOS, PDIP24, 0.300 INCH, PLASTIC, DIP-24	Field Programmable Gate Array, 62.5MHz, CMOS, PQCC28,	Field Programmable Gate Array, 62.5MHz, CMOS, PDIP24,	EE PLD, 20ns, CMOS, PQCC28, PLASTIC, LCC-28	Field Programmable Gate Array, 62.5MHz, CMOS, CDIP24,	EE PLD, 20ns, CMOS, CDIP24, 0.300 INCH, CERAMIC, DIP-24
Is it Rohs certified?	incompatible	incompatible	incompatible	incompatible	incompatible	incompatible
Maker	AMI Semiconductor	AMI Semiconductor	AMI Semiconductor	AMI Semiconductor	AMI Semiconductor	AMI Semiconductor
Reach Compliance Code	unknown	unknown	unknown	unknown	unknown	unknown
maximum clock frequency	41.6 MHz	62.5 MHz	62.5 MHz	41.6 MHz	62.5 MHz	41.6 MHz
JESD-30 code	R-PDIP-T24	S-PQCC-J28	R-PDIP-T24	S-PQCC-J28	R-XDIP-T24	R-CDIP-T24
JESD-609 code	e0	e0	e0	e0	e0	e0
Number of entries	22	22	22	22	22	22
Output times	20	20	20	20	20	20
Number of terminals	24	28	24	28	24	24
Maximum operating temperature	70 °C	70 °C	70 °C	70 °C	70 °C	70 °C
Package body material	PLASTIC/EPOXY	PLASTIC/EPOXY	PLASTIC/EPOXY	PLASTIC/EPOXY	CERAMIC	CERAMIC, METAL-SEALED COFIRED
encapsulated code	DIP	QCCJ	DIP	QCCJ	DIP	DIP
Encapsulate equivalent code	DIP24,.3	LDCC28,.5SQ	DIP24,.3	LDCC28,.5SQ	DIP24,.3	DIP24,.3
Package shape	RECTANGULAR	SQUARE	RECTANGULAR	SQUARE	RECTANGULAR	RECTANGULAR
Package form	IN-LINE	CHIP CARRIER	IN-LINE	CHIP CARRIER	IN-LINE	IN-LINE
power supply	5 V	5 V	5 V	5 V	5 V	5 V
Programmable logic type	EE PLD	FIELD PROGRAMMABLE GATE ARRAY	FIELD PROGRAMMABLE GATE ARRAY	EE PLD	FIELD PROGRAMMABLE GATE ARRAY	EE PLD
Certification status	Not Qualified	Not Qualified	Not Qualified	Not Qualified	Not Qualified	Not Qualified
Nominal supply voltage	5 V	5 V	5 V	5 V	5 V	5 V
surface mount	NO	YES	NO	YES	NO	NO
technology	CMOS	CMOS	CMOS	CMOS	CMOS	CMOS
Temperature level	COMMERCIAL	COMMERCIAL	COMMERCIAL	COMMERCIAL	COMMERCIAL	COMMERCIAL
Terminal surface	Tin/Lead (Sn/Pb)	Tin/Lead (Sn/Pb)	Tin/Lead (Sn/Pb)	Tin/Lead (Sn/Pb)	Tin/Lead (Sn/Pb)	Tin/Lead (Sn/Pb)
Terminal form	THROUGH-HOLE	J BEND	THROUGH-HOLE	J BEND	THROUGH-HOLE	THROUGH-HOLE
Terminal pitch	2.54 mm	1.27 mm	2.54 mm	1.27 mm	2.54 mm	2.54 mm
Terminal location	DUAL	QUAD	DUAL	QUAD	DUAL	DUAL

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