IDT70T659S12DRG datasheet, PDF

Datasheet> All Categories > storage> storage> IDT70T659S12DRG

IDT70T659S12DRG: DescriptionDual-Port SRAM, 128KX36, 12ns, CMOS, PQFP208, 28 X 28 MM, 3.50 MM PITCH, GREEN, PLASTIC, QFP-208; Categorystorage storage; File Size232KB，27 Pages; ManufacturerIDT (Integrated Device Technology); Environmental Compliance

Download Datasheet Parametric View All

IDT70T659S12DRG Overview

Dual-Port SRAM, 128KX36, 12ns, CMOS, PQFP208, 28 X 28 MM, 3.50 MM PITCH, GREEN, PLASTIC, QFP-208

IDT70T659S12DRG Parametric

Parameter Name	Attribute value
Is it lead-free?	Lead free
Is it Rohs certified?	conform to
Maker	IDT (Integrated Device Technology)
Parts packaging code	QFP
package instruction	FQFP, QFP208,1.2SQ,20
Contacts	208
Reach Compliance Code	compliant
ECCN code	3A991.B.2.A
Maximum access time	12 ns
I/O type	COMMON
JESD-30 code	S-PQFP-G208
JESD-609 code	e3
length	28 mm
memory density	4718592 bit
Memory IC Type	DUAL-PORT SRAM
memory width	36
Humidity sensitivity level	3
Number of functions	1
Number of ports	2
Number of terminals	208
word count	131072 words
character code	128000
Operating mode	ASYNCHRONOUS
Maximum operating temperature	70 °C
Minimum operating temperature
organize	128KX36
Output characteristics	3-STATE
Package body material	PLASTIC/EPOXY
encapsulated code	FQFP
Encapsulate equivalent code	QFP208,1.2SQ,20
Package shape	SQUARE
Package form	FLATPACK, FINE PITCH
Parallel/Serial	PARALLEL
Peak Reflow Temperature (Celsius)	260
power supply	2.5,2.5/3.3 V
Certification status	Not Qualified
Maximum seat height	4.1 mm
Maximum standby current	0.01 A
Minimum standby current	2.4 V
Maximum slew rate	0.355 mA
Maximum supply voltage (Vsup)	2.6 V
Minimum supply voltage (Vsup)	2.4 V
Nominal supply voltage (Vsup)	2.5 V
surface mount	YES
technology	CMOS
Temperature level	COMMERCIAL
Terminal surface	Matte Tin (Sn)
Terminal form	GULL WING
Terminal pitch	0.5 mm
Terminal location	QUAD
Maximum time at peak reflow temperature	30
width	28 mm

Preview

Download Datasheet

View All

◆

Features

HIGH-SPEED 2.5V

256/128K x 36

ASYNCHRONOUS DUAL-PORT

STATIC RAM

WITH 3.3V 0R 2.5V INTERFACE

◆

IDT70T651/9S

◆

True Dual-Port memory cells which allow simultaneous

access of the same memory location

High-speed access

– Commercial: 8/10/12/15ns (max.)

– Industrial: 10/12ns (max.)

RapidWrite Mode simplifies high-speed consecutive write

cycles

Dual chip enables allow for depth expansion without

external logic

IDT70T651/9 easily expands data bus width to 72 bits or

more using the Master/Slave select when cascading more

than one device

M/S = V

for

BUSY

output flag on Master,

M/S = V

for

BUSY

input on Slave

Busy and Interrupt Flags

◆

On-chip port arbitration logic

Full on-chip hardware support of semaphore signaling

between ports

Fully asynchronous operation from either port

Separate byte controls for multiplexed bus and bus

matching compatibility

Sleep Mode Inputs on both ports

Supports JTAG features compliant to IEEE 1149.1

Single 2.5V (±100mV) power supply for core

LVTTL-compatible, selectable 3.3V (±150mV)/2.5V (±100mV)

power supply for I/Os and control signals on each port

Available in a 256-ball Ball Grid Array, 208-pin Plastic Quad

Flatpack and 208-ball fine pitch Ball Grid Array.

Industrial temperature range (–40°C to +85°C) is available

for selected speeds

Green parts available, see ordering information

Functional Block Diagram

BBBB

EEEE

3210

R RRR

Dout0-8_L

Dout0-8_R

Dout9-17_L

Dout9-17_R

Dout18-26_L Dout18-26_R

Dout27-35_L Dout27-35_R

256/128K x 36

MEMORY

ARRAY

I/O

0L-

I/O

35L

Di n_L

Di n_R

I/O

0R -

I/O

35R

17L(1)

Address

Decoder

ADDR_L

ADDR_R

Address

Decoder

17R(1)

R/W

BUSY

L (2,3)

SEM

INT

L(3)

(4)

ARBITRATION

INTERRUPT

SEMAPHORE

LOGIC

R/W

TDI

TD O

JTAG

TC K

TMS

TRST

M/S

BUSY

R(2,3)

SEM

INT

R(3)

(4)

NOTES:

1. Address A

17x

is a NC for IDT70T659.

BUSY

is an input as a Slave (M/S=V

) and an output when it is a Master (M/S=V

BUSY

and

INT

are non-tri-state totem-pole outputs (push-pull).

4. The sleep mode pin shuts off all dynamic inputs, except JTAG inputs, when asserted. OPTx,

INTx,

M/S and the sleep

mode pins themselves (ZZx) are not affected during sleep mode.

CONTROL

LOGIC

4869 drw 01

JANUARY 2006

DSC-5632/5

Recommended Resources

Blood pressure sensing circuit diagram of BP01 pressure sensor

Push-pull power amplifier circuit

High current NOT gate driving a grounded load

LM3578A used as a boost regulator circuit diagram

Digital display experimental power supply circuit diagram

24 Mbit data path

Jinlong Electronics FAE Li Xinping (responsible for Marvell series products, supporting PXA270, PXA3XX series CPU): Hello everyone, I am Li Xinping, FAE of Jinlong Electronics, responsible for the technical support of Marvell Xscale series CPU. Currently, Jinlong Electronics provides technical support and chip sale...; wto4tnt Embedded System

【Reference Design】Solutions for circuit breakers: [i=s]This post was last edited by qwqwqw2088 on 2020-1-29 10:30[/i]Design Considerations Our integrated circuits and reference designs help you protect grid assets by creating circuit breakers that ca...; qwqwqw2088 Analogue and Mixed Signal

[NXP Rapid IoT Review] + Essential content for web-based rapid design: NXP Rapid IoT's web-based rapid design platform is quite good. This platform is provided by Atmosphere, and the introduction on Atmosphere's website is more systematic and detailed than that on the NX...; bjemt RF/Wirelessly

Linear NTC Temperature Sensor Usage Guide: [align=center][align=center][b][font=宋体][size=12pt]LINE[/size][/font][/b][b][size=12pt][font=Times New Roman ] [/font][/size][/b][b][font=宋体][size=12pt]性[/size][/font][/b][b][size=12pt][font= Times Ne...; tonytyping Sensor

RTL buffer insertion and fault classification techniques to verify untested functions: At present, the design cycle of integrated circuits is required to be shorter, but the scale is larger and the structure is more complex. Improving the test coverage of chips has become one of the foc...; 26979746 DSP and ARM Processors

If 8025 is frequently reset, will the clock be slow?: 8025 requires communication to be completed within 0.95 seconds. If it is not completed, the 8025 bus time overflow reset, will it cause the 8025 clock to slow down? ? ? Can you analyze it?...; newnew0601 MCU

Shortcut: E0 E1 E2 E3 E4 E5 E6 E7 E8 E9 EA EB EC ED EE EF EG EH EI EJ EK EL EM EN EO EP EQ ER ES ET EU EV EW EX EY EZ F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 FA FB FC FD FE FF FG FH FI FJ FK FL FM FN FO FP FQ FR FS FT FU FV FW FX FY FZ G0 G1 G2 G3 G4 G5 G6 G7 G8 G9 GA GB GC GD GE GF GG GH GI GJ GK GL GM GN GO GP GQ GR GS GT GU GV GW GX GZ H0 H1 H2 H3 H4 H5 H6 H7 H8 HA HB HC HD HE HF HG HH HI HJ HK HL HM HN HO HP HQ HR HS HT HU HV HW HX HY HZ I1 I2 I3 I4 I5 I6 I7 IA IB IC ID IE IF IG IH II IK IL IM IN IO IP IQ IR IS IT IU IV IW IX J0 J1 J2 J6 J7 JA JB JC JD JE JF JG JH JJ JK JL JM JN JP JQ JR JS JT JV JW JX JZ K0 K1 K2 K3 K4 K5 K6 K7 K8 K9 KA KB KC KD KE KF KG KH KI KJ KK KL KM KN KO KP KQ KR KS KT KU KV KW KX KY KZ

Popular Components