IDT71128S20Y datasheet, PDF - EEWORLD Datasheet

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IDT71128S20Y: DescriptionStandard SRAM, 256KX4, 20ns, CMOS, PDSO32, 0.400 INCH, PLASTIC, SOJ-32; Categorystorage storage; File Size79KB，8 Pages; ManufacturerIDT (Integrated Device Technology)

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IDT71128S20Y Overview

Standard SRAM, 256KX4, 20ns, CMOS, PDSO32, 0.400 INCH, PLASTIC, SOJ-32

IDT71128S20Y Parametric

Parameter Name	Attribute value
Is it Rohs certified?	incompatible
Maker	IDT (Integrated Device Technology)
Parts packaging code	SOJ
package instruction	0.400 INCH, PLASTIC, SOJ-32
Contacts	32
Reach Compliance Code	not_compliant
ECCN code	3A991.B.2.B
Maximum access time	20 ns
I/O type	COMMON
JESD-30 code	R-PDSO-J32
JESD-609 code	e0
length	20.955 mm
memory density	1048576 bit
Memory IC Type	STANDARD SRAM
memory width	4
Humidity sensitivity level	3
Number of functions	1
Number of ports	1
Number of terminals	32
word count	262144 words
character code	256000
Operating mode	ASYNCHRONOUS
Maximum operating temperature	70 °C
Minimum operating temperature
organize	256KX4
Output characteristics	3-STATE
Exportable	YES
Package body material	PLASTIC/EPOXY
encapsulated code	SOJ
Encapsulate equivalent code	SOJ32,.44
Package shape	RECTANGULAR
Package form	SMALL OUTLINE
Parallel/Serial	PARALLEL
Peak Reflow Temperature (Celsius)	225
power supply	5 V
Certification status	Not Qualified
Maximum seat height	3.683 mm
Maximum standby current	0.01 A
Minimum standby current	4.5 V
Maximum slew rate	0.145 mA
Maximum supply voltage (Vsup)	5.5 V
Minimum supply voltage (Vsup)	4.5 V
Nominal supply voltage (Vsup)	5 V
surface mount	YES
technology	CMOS
Temperature level	COMMERCIAL
Terminal surface	Tin/Lead (Sn85Pb15)
Terminal form	J BEND
Terminal pitch	1.27 mm
Terminal location	DUAL
Maximum time at peak reflow temperature	30
width	10.16 mm

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CMOS Static RAM

1 Meg (256K x 4-Bit)

Revolutionary Pinout

Features

IDT71128

Description

The IDT71128 is a 1,048,576-bit high-speed static RAM

organized as 256K x 4. It is fabricated using IDT’s high-perfor-

mance, high-reliability CMOS technology. This state-of-the-art

technology, combined with innovative circuit design techniques,

provides a cost-effective solution for high-speed memory needs.

The JEDEC centerpower/GND pinout reduces noise generation

and improves system performance.

The IDT71128 has an output enable pin which operates as fast

as 6ns, with address access times as fast as 12ns available. All

bidirectional inputs and outputs of the IDT71128 are TTL-compat-

ible and operation is from a single 5V supply. Fully static asyn-

chronous circuitry is used; no clocks or refreshes are required for

operation.

The IDT71128 is packaged in a 32-pin 400 mil Plastic SOJ.

256K x 4 advanced high-speed CMOS static RAM

JEDEC revolutionary pinout (center power/GND) for

reduced noise.

Equal access and cycle times

— Commercial and Industrial: 12/15/20ns

One Chip Select plus one Output Enable pin

Bidirectional inputs and outputs directly

TTL-compatible

Low power consumption via chip deselect

Available in a 32-pin 400 mil Plastic SOJ.

Functional Block Diagram

ADDRESS

DECODER

1,048,576-BIT

MEMORY

ARRAY

I/O

- I/O

I/O CONTROL

CONTROL

LOGIC

3483 drw 01

FEBRUARY 2001

DSC-3483/09

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