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723633L12PF8

Description
TQFP-128, Reel
Categorystorage    storage   
File Size343KB,29 Pages
ManufacturerIDT (Integrated Device Technology)
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723633L12PF8 Overview

TQFP-128, Reel

723633L12PF8 Parametric

Parameter NameAttribute value
Brand NameIntegrated Device Technology
Is it lead-free?Contains lead
Is it Rohs certified?incompatible
MakerIDT (Integrated Device Technology)
Parts packaging codeTQFP
package instructionTQFP-128
Contacts128
Manufacturer packaging codePK128
Reach Compliance Codenot_compliant
ECCN codeEAR99
Maximum access time8 ns
Other featuresMAIL BOX
Maximum clock frequency (fCLK)83 MHz
period time12 ns
JESD-30 codeR-PQFP-G128
JESD-609 codee0
length20 mm
memory density18432 bit
Memory IC TypeOTHER FIFO
memory width36
Humidity sensitivity level3
Number of functions1
Number of terminals128
word count512 words
character code512
Operating modeSYNCHRONOUS
Maximum operating temperature70 °C
Minimum operating temperature
organize512X36
ExportableYES
Package body materialPLASTIC/EPOXY
encapsulated codeLFQFP
Encapsulate equivalent codeQFP128,.63X.87,20
Package shapeRECTANGULAR
Package formFLATPACK, LOW PROFILE, FINE PITCH
Parallel/SerialPARALLEL
Peak Reflow Temperature (Celsius)225
power supply5 V
Certification statusNot Qualified
Maximum seat height1.6 mm
Maximum standby current0.001 A
Maximum supply voltage (Vsup)5.5 V
Minimum supply voltage (Vsup)4.5 V
Nominal supply voltage (Vsup)5 V
surface mountYES
technologyCMOS
Temperature levelCOMMERCIAL
Terminal surfaceTin/Lead (Sn85Pb15)
Terminal formGULL WING
Terminal pitch0.5 mm
Terminal locationQUAD
Maximum time at peak reflow temperatureNOT SPECIFIED
width14 mm
CMOS BUS-MATCHING SyncFIFO
TM
256 x 36, 512 x 36, 1,024 x 36
FEATURES:
IDT723623
IDT723633
IDT723643
LEAD FINISH (SnPb) ARE IN EOL PROCESS - LAST TIME BUY EXPIRES JUNE 15, 2018
Memory storage capacity:
IDT723623 – 256 x 36
IDT723633 – 512 x 36
IDT723643 – 1,024 x 36
Clocked FIFO buffering data from Port A to Port B
Clock frequencies up to 83 MHz (8 ns access time)
IDT Standard timing (using
EF
and
FF)
or First Word Fall
Through Timing (using OR and IR flag functions)
Programmable Almost-Empty and Almost-Full flags; each has
three default offsets (8, 16 and 64)
Serial or parallel programming of partial flags
Port B bus sizing of 36 bits (long word), 18 bits (word) and 9 bits
(byte)
Big- or Little-Endian format for word and byte bus sizes
Reset clears data and configures FIFO, Partial Reset clears data
but retains configuration settings
Mailbox bypass registers for each FIFO
Free-running CLKA and CLKB may be asynchronous or
coincident (simultaneous reading and writing of data on a single
clock edge is permitted)
Easily expandable in width and depth
Auto power down minimizes power dissipation
Available in a space-saving 128-pin Thin Quad Flatpack (TQFP)
Green parts available, see ordering information
DESCRIPTION:
The IDT723623/723633/723643 are monolithic, high-speed, low-power,
CMOS unidirectional Synchronous (clocked) FIFO memories which support
clock frequencies up to 83 MHz and have read access times as fast as 8 ns.
FUNCTIONAL BLOCK DIAGRAM
MBF1
Mail 1
Register
Port-A
Control
Logic
Bus-
Matching
Input
Register
Output
Register
CLKA
CSA
W/RA
ENA
MBA
RS1
RS2
PRS
FIFO1
Mail1,
Mail2,
Reset
Logic
36
36
RAM ARRAY
256 x 36
512 x 36
1,024 x 36
36
36
A
0
-A
35
Write
Pointer
Read
Pointer
B
0
-B
35
FF/IR
AF
Status Flag
Logic
EF/OR
AE
36
36
SPM
FS0/SD
FS1/SEN
Programmable Flag
Offset Registers
10
Timing
Mode
Port-B
Control
Logic
Mail 2
Register
MBF2
IDT and the IDT logo are registered trademarks of Integrated Device Technology, Inc. SyncFIFO is a trademark of Integrated Device Technology, Inc.
FWFT
CLKB
CSB
W/RB
ENB
MBB
BE
BM
SIZE
3269 drw01
COMMERCIAL TEMPERATURE RANGE
1
©
2018 Integrated Device Technology, Inc.
All rights reserved. Product specifications subject to change without notice.
MARCH 2018
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