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74AUP1G74GD

Description
Low-power D-type flip-flop with set and reset; positive-edge trigger
Categorylogic    logic   
File Size102KB,24 Pages
ManufacturerNXP
Websitehttps://www.nxp.com
Environmental Compliance
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74AUP1G74GD Overview

Low-power D-type flip-flop with set and reset; positive-edge trigger

74AUP1G74GD Parametric

Parameter NameAttribute value
Source Url Status Check Date2013-06-14 00:00:00
Is it lead-free?Lead free
Is it Rohs certified?conform to
MakerNXP
Parts packaging codeSON
package instructionVSON, SOLCC8,.11,20
Contacts8
Reach Compliance Codecompli
seriesAUP/ULP/V
JESD-30 codeR-PDSO-N8
JESD-609 codee4
length3 mm
Load capacitance (CL)30 pF
Logic integrated circuit typeD FLIP-FLOP
Maximum Frequency@Nom-Su150000000 Hz
MaximumI(ol)0.0017 A
Humidity sensitivity level1
Number of digits1
Number of functions1
Number of terminals8
Maximum operating temperature125 °C
Minimum operating temperature-40 °C
Output polarityCOMPLEMENTARY
Package body materialPLASTIC/EPOXY
encapsulated codeVSON
Encapsulate equivalent codeSOLCC8,.11,20
Package shapeRECTANGULAR
Package formSMALL OUTLINE, VERY THIN PROFILE
method of packingTAPE AND REEL
Peak Reflow Temperature (Celsius)260
power supply1.2/3.3 V
propagation delay (tpd)23.3 ns
Certification statusNot Qualified
Maximum seat height0.5 mm
Maximum supply voltage (Vsup)3.6 V
Minimum supply voltage (Vsup)0.8 V
Nominal supply voltage (Vsup)1.1 V
surface mountYES
technologyCMOS
Temperature levelAUTOMOTIVE
Terminal surfaceNickel/Palladium/Gold (Ni/Pd/Au)
Terminal formNO LEAD
Terminal pitch0.5 mm
Terminal locationDUAL
Maximum time at peak reflow temperature30
Trigger typePOSITIVE EDGE
width2 mm
minfmax510 MHz
74AUP1G74
Low-power D-type flip-flop with set and reset; positive-edge
trigger
Rev. 04 — 3 June 2008
Product data sheet
1. General description
The 74AUP1G74 provides a low-power, low-voltage single positive-edge triggered D-type
flip-flop with individual data (D), clock (CP), set (SD) and reset (RD) inputs and
complementary Q and Q outputs. The SD and RD are asynchronous active LOW inputs
and operate independently of the clock input. Information on the data input is transferred
to the Q output on the LOW-to-HIGH transition of the clock pulse. The D input must be
stable one set-up time prior to the LOW-to-HIGH clock transition for predictable operation.
Schmitt trigger action at all inputs makes the circuit tolerant to slower input rise and fall
times across the entire V
CC
range from 0.8 V to 3.6 V.
This device ensures a very low static and dynamic power consumption across the entire
V
CC
range from 0.8 V to 3.6 V.
This device is fully specified for partial power-down applications using I
OFF
. The I
OFF
circuitry disables the output, preventing the damaging backflow current through the device
when it is powered down.
2. Features
I
Wide supply voltage range from 0.8 V to 3.6 V
I
High noise immunity
I
Complies with JEDEC standards:
N
JESD8-12 (0.8 V to 1.3 V)
N
JESD8-11 (0.9 V to 1.65 V)
N
JESD8-7 (1.2 V to 1.95 V)
N
JESD8-5 (1.8 V to 2.7 V)
N
JESD8-B (2.7 V to 3.6 V)
I
ESD protection:
N
HBM JESD22-A114E Class 3A exceeds 5000 V
N
MM JESD22-A115-A exceeds 200 V
N
CDM JESD22-C101C exceeds 1000 V
I
Low static power consumption; I
CC
= 0.9
µA
(maximum)
I
Latch-up performance exceeds 100 mA per JESD 78 Class II
I
Inputs accept voltages up to 3.6 V
I
Low noise overshoot and undershoot < 10 % of V
CC
I
I
OFF
circuitry provides partial Power-down mode operation
I
Multiple package options
I
Specified from
−40 °C
to +85
°C
and
−40 °C
to +125
°C

74AUP1G74GD Related Products

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Reach Compliance Code compli compli compli unknow compli
Is it Rohs certified? conform to conform to conform to - conform to
Maker NXP - NXP - NXP
Parts packaging code SON TSSOP SON - QFN
package instruction VSON, SOLCC8,.11,20 VSSOP, TSSOP8,.12,20 VSON, SOLCC8,.04,20 - HVQCCN, LCC8,.06SQ,20
Contacts 8 8 8 - 8
series AUP/ULP/V AUP/ULP/V AUP/ULP/V - AUP/ULP/V
JESD-30 code R-PDSO-N8 R-PDSO-G8 R-PDSO-N8 - S-PQCC-N8
JESD-609 code e4 e4 e3 - e4
length 3 mm 2.3 mm 1.95 mm - 1.6 mm
Load capacitance (CL) 30 pF 30 pF 30 pF - 30 pF
Logic integrated circuit type D FLIP-FLOP D FLIP-FLOP D FLIP-FLOP - D FLIP-FLOP
Maximum Frequency@Nom-Su 150000000 Hz 70000000 Hz 70000000 Hz - 70000000 Hz
MaximumI(ol) 0.0017 A 0.0017 A 0.0017 A - 0.0017 A
Humidity sensitivity level 1 1 1 - 1
Number of digits 1 1 1 - 1
Number of functions 1 1 1 - 1
Number of terminals 8 8 8 - 8
Maximum operating temperature 125 °C 125 °C 125 °C - 125 °C
Minimum operating temperature -40 °C -40 °C -40 °C - -40 °C
Output polarity COMPLEMENTARY COMPLEMENTARY COMPLEMENTARY - COMPLEMENTARY
Package body material PLASTIC/EPOXY PLASTIC/EPOXY PLASTIC/EPOXY - PLASTIC/EPOXY
encapsulated code VSON VSSOP VSON - HVQCCN
Encapsulate equivalent code SOLCC8,.11,20 TSSOP8,.12,20 SOLCC8,.04,20 - LCC8,.06SQ,20
Package shape RECTANGULAR RECTANGULAR RECTANGULAR - SQUARE
Package form SMALL OUTLINE, VERY THIN PROFILE SMALL OUTLINE, VERY THIN PROFILE, SHRINK PITCH SMALL OUTLINE, VERY THIN PROFILE - CHIP CARRIER, HEAT SINK/SLUG, VERY THIN PROFILE
method of packing TAPE AND REEL TAPE AND REEL TAPE AND REEL - TAPE AND REEL
Peak Reflow Temperature (Celsius) 260 260 260 - 260
power supply 1.2/3.3 V 1.2/3.3 V 1.2/3.3 V - 1.2/3.3 V
propagation delay (tpd) 23.3 ns 23.3 ns 23.3 ns - 23.3 ns
Certification status Not Qualified Not Qualified Not Qualified - Not Qualified
Maximum seat height 0.5 mm 1 mm 0.5 mm - 0.5 mm
Maximum supply voltage (Vsup) 3.6 V 3.6 V 3.6 V - 3.6 V
Minimum supply voltage (Vsup) 0.8 V 0.8 V 0.8 V - 0.8 V
Nominal supply voltage (Vsup) 1.1 V 1.1 V 1.1 V - 1.1 V
surface mount YES YES YES - YES
technology CMOS CMOS CMOS - CMOS
Temperature level AUTOMOTIVE AUTOMOTIVE AUTOMOTIVE - AUTOMOTIVE
Terminal surface Nickel/Palladium/Gold (Ni/Pd/Au) Nickel/Palladium/Gold (Ni/Pd/Au) Tin (Sn) - NICKEL PALLADIUM GOLD
Terminal form NO LEAD GULL WING NO LEAD - NO LEAD
Terminal pitch 0.5 mm 0.5 mm 0.5 mm - 0.5 mm
Terminal location DUAL DUAL DUAL - QUAD
Maximum time at peak reflow temperature 30 30 30 - 30
Trigger type POSITIVE EDGE POSITIVE EDGE POSITIVE EDGE - POSITIVE EDGE
width 2 mm 2 mm 1 mm - 1.6 mm
minfmax 510 MHz 510 MHz 510 MHz - 510 MHz
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