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74LVC2G08DC

Description
Dual 2-input AND gate
Categorylogic    logic   
File Size81KB,16 Pages
ManufacturerNXP
Websitehttps://www.nxp.com
Environmental Compliance
Download Datasheet Parametric Compare View All

74LVC2G08DC Overview

Dual 2-input AND gate

74LVC2G08DC Parametric

Parameter NameAttribute value
Is it lead-free?Lead free
Is it Rohs certified?conform to
MakerNXP
Parts packaging codeTSSOP
package instruction2.30 MM, PLASTIC, MO-187, SOT765-1, VSSOP-8
Contacts8
Reach Compliance Codecompli
ECCN codeEAR99
seriesLVC/LCX/Z
JESD-30 codeR-PDSO-G8
JESD-609 codee4
length2.3 mm
Load capacitance (CL)50 pF
Logic integrated circuit typeAND GATE
MaximumI(ol)0.024 A
Humidity sensitivity level1
Number of functions2
Number of entries2
Number of terminals8
Maximum operating temperature125 °C
Minimum operating temperature-40 °C
Package body materialPLASTIC/EPOXY
encapsulated codeVSSOP
Encapsulate equivalent codeTSSOP8,.12,20
Package shapeRECTANGULAR
Package formSMALL OUTLINE, VERY THIN PROFILE, SHRINK PITCH
method of packingTAPE AND REEL
Peak Reflow Temperature (Celsius)260
power supply3.3 V
Prop。Delay @ Nom-Su5.9 ns
propagation delay (tpd)11.3 ns
Certification statusNot Qualified
Schmitt triggerNO
Maximum seat height1 mm
Maximum supply voltage (Vsup)5.5 V
Minimum supply voltage (Vsup)1.65 V
Nominal supply voltage (Vsup)1.8 V
surface mountYES
technologyCMOS
Temperature levelAUTOMOTIVE
Terminal surfaceNickel/Palladium/Gold (Ni/Pd/Au)
Terminal formGULL WING
Terminal pitch0.5 mm
Terminal locationDUAL
Maximum time at peak reflow temperature30
width2 mm
74LVC2G08
Dual 2-input AND gate
Rev. 08 — 9 June 2008
Product data sheet
1. General description
The 74LVC2G08 provides a 2-input AND gate function.
Inputs can be driven from either 3.3 V or 5 V devices. This feature allows the use of the
74LVC2G08 as a translator in a mixed 3.3 V and 5 V environment.
This device is fully specified for partial power-down applications using I
OFF
. The I
OFF
circuitry disables the output, preventing a damaging backflow current through the device
when it is powered down.
2. Features
I
I
I
I
I
I
Wide supply voltage range from 1.65 V to 5.5 V
5 V tolerant outputs for interfacing with 5 V logic
High noise immunity
±24
mA output drive (V
CC
= 3.0 V)
CMOS low power consumption
Complies with JEDEC standard:
N
JESD8-7 (1.65 V to 1.95 V)
N
JESD8-5 (2.3 V to 2.7 V)
N
JESD8-B/JESD36 (2.7 V to 3.6 V)
Latch-up performance exceeds 250 mA
Direct interface with TTL levels
Inputs accept voltages up to 5 V
ESD protection:
N
HBM JESD22-A114E exceeds 2000 V
N
MM JESD22-A115-A exceeds 200 V
Multiple package options
Specified from
−40 °C
to +85
°C
and
−40 °C
to +125
°C
I
I
I
I
I
I

74LVC2G08DC Related Products

74LVC2G08DC 74LVC2G08GM 74LVC2G08GD 74LVC2G08GT
Description Dual 2-input AND gate Dual 2-input AND gate Dual 2-input AND gate Dual 2-input AND gate
Is it Rohs certified? conform to conform to conform to conform to
Maker NXP NXP NXP NXP
Parts packaging code TSSOP QFN SON SON
package instruction 2.30 MM, PLASTIC, MO-187, SOT765-1, VSSOP-8 VBCC, LCC8,.06SQ,20 VSON, SOLCC8,.11,20 1 X 1.95 MM, 0.50 MM HEIGHT, PLASTIC, MO-252, SOT833-1, SON-8
Contacts 8 8 8 8
Reach Compliance Code compli compli compli compli
series LVC/LCX/Z LVC/LCX/Z LVC/LCX/Z LVC/LCX/Z
JESD-30 code R-PDSO-G8 S-PBCC-B8 R-PDSO-N8 R-PDSO-N8
JESD-609 code e4 e4 e4 e3
length 2.3 mm 1.6 mm 3 mm 1.95 mm
Load capacitance (CL) 50 pF 50 pF 50 pF 50 pF
Logic integrated circuit type AND GATE AND GATE AND GATE AND GATE
MaximumI(ol) 0.024 A 0.024 A 0.024 A 0.024 A
Humidity sensitivity level 1 1 1 1
Number of functions 2 2 2 2
Number of entries 2 2 2 2
Number of terminals 8 8 8 8
Maximum operating temperature 125 °C 125 °C 125 °C 125 °C
Minimum operating temperature -40 °C -40 °C -40 °C -40 °C
Package body material PLASTIC/EPOXY PLASTIC/EPOXY PLASTIC/EPOXY PLASTIC/EPOXY
encapsulated code VSSOP VBCC VSON VSON
Encapsulate equivalent code TSSOP8,.12,20 LCC8,.06SQ,20 SOLCC8,.11,20 SOLCC8,.04,20
Package shape RECTANGULAR SQUARE RECTANGULAR RECTANGULAR
Package form SMALL OUTLINE, VERY THIN PROFILE, SHRINK PITCH CHIP CARRIER, VERY THIN PROFILE SMALL OUTLINE, VERY THIN PROFILE SMALL OUTLINE, VERY THIN PROFILE
method of packing TAPE AND REEL TAPE AND REEL TAPE AND REEL TAPE AND REEL
Peak Reflow Temperature (Celsius) 260 260 260 260
power supply 3.3 V 3.3 V 3.3 V 3.3 V
Prop。Delay @ Nom-Su 5.9 ns 5.9 ns 5.9 ns 5.9 ns
propagation delay (tpd) 11.3 ns 11.3 ns 11.3 ns 11.3 ns
Certification status Not Qualified Not Qualified Not Qualified Not Qualified
Schmitt trigger NO NO NO NO
Maximum seat height 1 mm 0.5 mm 0.5 mm 0.5 mm
Maximum supply voltage (Vsup) 5.5 V 5.5 V 5.5 V 5.5 V
Minimum supply voltage (Vsup) 1.65 V 1.65 V 1.65 V 1.65 V
Nominal supply voltage (Vsup) 1.8 V 1.8 V 1.8 V 1.8 V
surface mount YES YES YES YES
technology CMOS CMOS CMOS CMOS
Temperature level AUTOMOTIVE AUTOMOTIVE AUTOMOTIVE AUTOMOTIVE
Terminal surface Nickel/Palladium/Gold (Ni/Pd/Au) Nickel/Palladium/Gold (Ni/Pd/Au) Nickel/Palladium/Gold (Ni/Pd/Au) Tin (Sn)
Terminal form GULL WING BUTT NO LEAD NO LEAD
Terminal pitch 0.5 mm 0.5 mm 0.5 mm 0.5 mm
Terminal location DUAL BOTTOM DUAL DUAL
Maximum time at peak reflow temperature 30 30 30 30
width 2 mm 1.6 mm 2 mm 1 mm
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