74LVC2G08
Dual 2-input AND gate
Rev. 08 — 9 June 2008
Product data sheet
1. General description
The 74LVC2G08 provides a 2-input AND gate function.
Inputs can be driven from either 3.3 V or 5 V devices. This feature allows the use of the
74LVC2G08 as a translator in a mixed 3.3 V and 5 V environment.
This device is fully specified for partial power-down applications using I
OFF
. The I
OFF
circuitry disables the output, preventing a damaging backflow current through the device
when it is powered down.
2. Features
I
I
I
I
I
I
Wide supply voltage range from 1.65 V to 5.5 V
5 V tolerant outputs for interfacing with 5 V logic
High noise immunity
±24
mA output drive (V
CC
= 3.0 V)
CMOS low power consumption
Complies with JEDEC standard:
N
JESD8-7 (1.65 V to 1.95 V)
N
JESD8-5 (2.3 V to 2.7 V)
N
JESD8-B/JESD36 (2.7 V to 3.6 V)
Latch-up performance exceeds 250 mA
Direct interface with TTL levels
Inputs accept voltages up to 5 V
ESD protection:
N
HBM JESD22-A114E exceeds 2000 V
N
MM JESD22-A115-A exceeds 200 V
Multiple package options
Specified from
−40 °C
to +85
°C
and
−40 °C
to +125
°C
I
I
I
I
I
I
NXP Semiconductors
74LVC2G08
Dual 2-input AND gate
3. Ordering information
Table 1.
Ordering information
Package
Temperature range Name
74LVC2G08DP
74LVC2G08DC
74LVC2G08GT
74LVC2G08GD
74LVC2G08GM
−40 °C
to +125
°C
−40 °C
to +125
°C
−40 °C
to +125
°C
−40 °C
to +125
°C
−40 °C
to +125
°C
TSSOP8
VSSOP8
XSON8
XSON8U
XQFN8U
Description
plastic thin shrink small outline package; 8 leads;
body width 3 mm; lead length 0.5 mm
Version
SOT505-2
Type number
plastic very thin shrink small outline package; 8 leads; SOT765-1
body width 2.3 mm
plastic extremely thin small outline package; no leads; SOT833-1
8 terminals; body 1
×
1.95
×
0.5 mm
plastic extremely thin small outline package; no leads; SOT996-2
8 terminals; UTLP based; body 3
×
2
×
0.5 mm
plastic extremely thin quad flat package; no leads;
8 terminals; UTLP based; body 1.6
×
1.6
×
0.5 mm
SOT902-1
4. Marking
Table 2.
Marking codes
Marking code
V08
V08
V08
V08
V08
Type number
74LVC2G08DP
74LVC2G08DC
74LVC2G08GT
74LVC2G08GD
74LVC2G08GM
5. Functional diagram
&
1A
1B
2A
2B
1Y
2Y
&
001aah789
001aah788
Fig 1.
Logic symbol
Fig 2.
IEC logic symbol
A
Y
B
mna221
Fig 3.
Logic diagram (one gate)
74LVC2G08_8
© NXP B.V. 2008. All rights reserved.
Product data sheet
Rev. 08 — 9 June 2008
2 of 16
NXP Semiconductors
74LVC2G08
Dual 2-input AND gate
6. Pinning information
6.1 Pinning
74LVC2G08
1A
1
8
V
CC
1B
2
7
1Y
74LVC2G08
1A
1B
2Y
GND
1
2
3
4
001aae981
8
7
6
5
V
CC
1Y
2B
2A
2Y
3
6
2B
GND
4
5
2A
001aae982
Transparent top view
Fig 4.
Pin configuration SOT505-2 (TSSOP8) and
SOT765-1 (VSSOP8)
Fig 5.
Pin configuration SOT833-1 (XSON8)
74LVC2G08
terminal 1
index area
1Y
1
V
CC
8
74LVC2G08
1A
1B
2Y
GND
1
2
3
4
8
7
6
5
V
CC
7
1A
2B
1Y
2B
2A
2A
2
6
1B
3
4
5
2Y
GND
001aae983
001aai245
Transparent top view
Transparent top view
Fig 6.
Pin configuration SOT996-2 (XSON8U)
Fig 7.
Pin configuration SOT902-1 (XQFN8U)
6.2 Pin description
Table 3.
Symbol
Pin description
Pin
SOT505-2, SOT765-1,
SOT833-1 and SOT996-2
1A
1B
2Y
GND
2A
74LVC2G08_8
Description
SOT902-1
7
6
5
4
3
data input
data input
data output
ground (0 V)
data input
© NXP B.V. 2008. All rights reserved.
1
2
3
4
5
Product data sheet
Rev. 08 — 9 June 2008
3 of 16
NXP Semiconductors
74LVC2G08
Dual 2-input AND gate
Table 3.
Symbol
Pin description
…continued
Pin
SOT505-2, SOT765-1,
SOT833-1 and SOT996-2
SOT902-1
2
1
8
data input
data output
supply voltage
Description
2B
1Y
V
CC
6
7
8
7. Functional description
Table 4.
Input
nA
L
X
H
[1]
Function table
[1]
Output
nB
X
L
H
nY
L
L
H
H = HIGH voltage level; L = LOW voltage level; X = don’t care.
8. Limiting values
Table 5.
Limiting values
In accordance with the Absolute Maximum Rating System (IEC 60134). Voltages are referenced to GND (ground = 0 V).
Symbol
V
CC
V
I
V
O
I
IK
I
OK
I
O
I
CC
I
GND
T
stg
P
tot
[1]
[2]
[3]
Parameter
supply voltage
input voltage
output voltage
input clamping current
output clamping current
output current
supply current
ground current
storage temperature
total power dissipation
Conditions
[1]
Min
−0.5
−0.5
−0.5
−0.5
−50
-
-
-
−100
−65
Max
+6.5
+6.5
V
CC
+ 0.5
+6.5
-
±50
±50
100
-
+150
300
Unit
V
V
V
V
mA
mA
mA
mA
mA
°C
mW
Active mode
Power-down mode
V
I
< 0 V
V
O
< 0 V or V
O
> V
CC
V
O
= 0 V to V
CC
[1]
[1][2]
T
amb
=
−40 °C
to +125
°C
[3]
-
The input and output voltage ratings may be exceeded if the input and output current ratings are observed.
When V
CC
= 0 V (Power-down mode), the output voltage can be 5.5 V in normal condition.
For TSSOP8 package: above 55
°C
the value of P
tot
derates linearly at 2.5 mW/K.
For VSSOP8 package: above 110
°C
the value of P
tot
derates linearly at 8 mW/K.
For XSON8, XSON8U and XQFN8U packages: above 45
°C
the value of P
tot
derates linearly at 2.4 mW/K.
74LVC2G08_8
© NXP B.V. 2008. All rights reserved.
Product data sheet
Rev. 08 — 9 June 2008
4 of 16
NXP Semiconductors
74LVC2G08
Dual 2-input AND gate
9. Recommended operating conditions
Table 6.
Symbol
V
CC
V
I
V
O
T
amb
∆t/∆V
Operating conditions
Parameter
supply voltage
input voltage
output voltage
ambient temperature
input transition rise and fall rate
V
CC
= 1.65 V to 2.7 V
V
CC
= 2.7 V to 5.5 V
Active mode
Power-down mode
Conditions
Min
1.65
0
0
0
−40
-
-
Max
5.5
5.5
V
CC
5.5
+125
20
10
Unit
V
V
V
V
°C
ns/V
ns/V
10. Static characteristics
Table 7.
Static characteristics
At recommended operating conditions; voltages are referenced to GND (ground = 0 V).
Symbol Parameter
T
amb
=
−40 °C
to +85
°C
[1]
V
IH
HIGH-level input voltage
V
CC
= 1.65 V to 1.95 V
V
CC
= 2.3 V to 2.7 V
V
CC
= 2.7 V to 3.6 V
V
CC
= 4.5 V to 5.5 V
V
IL
LOW-level input voltage
V
CC
= 1.65 V to 1.95 V
V
CC
= 2.3 V to 2.7 V
V
CC
= 2.7 V to 3.6 V
V
CC
= 4.5 V to 5.5 V
V
OH
HIGH-level output voltage V
I
= V
IH
or V
IL
I
O
=
−100 µA;
V
CC
= 1.65 V to 5.5 V
I
O
=
−4
mA; V
CC
= 1.65 V
I
O
=
−8
mA; V
CC
= 2.3 V
I
O
=
−12
mA; V
CC
= 2.7 V
I
O
=
−24
mA; V
CC
= 3.0 V
I
O
=
−32
mA; V
CC
= 4.5 V
V
OL
LOW-level output voltage
V
I
= V
IH
or V
IL
I
O
= 100
µA;
V
CC
= 1.65 V to 5.5 V
I
O
= 4 mA; V
CC
= 1.65 V
I
O
= 8 mA; V
CC
= 2.3 V
I
O
= 12 mA; V
CC
= 2.7 V
I
O
= 24 mA; V
CC
= 3.0 V
I
O
= 32 mA; V
CC
= 4.5 V
I
I
I
OFF
input leakage current
V
I
= 5.5 V or GND; V
CC
= 0 V to 5.5 V
power-off leakage current V
I
or V
O
= 5.5 V; V
CC
= 0 V
-
-
-
-
-
-
-
-
-
0.08
0.14
0.19
0.37
0.43
±0.1
±0.1
0.1
0.45
0.3
0.4
0.55
0.55
±5
±10
V
V
V
V
V
V
µA
µA
V
CC
−
0.1
1.2
1.9
2.2
2.3
3.8
-
1.53
2.13
2.50
2.60
4.10
-
-
-
-
-
-
V
V
V
V
V
V
0.65
×
V
CC
-
1.7
2.0
0.7
×
V
CC
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
0.7
0.8
0.3
×
V
CC
V
V
V
V
V
V
V
Conditions
Min
Typ
Max
Unit
0.35
×
V
CC
V
74LVC2G08_8
© NXP B.V. 2008. All rights reserved.
Product data sheet
Rev. 08 — 9 June 2008
5 of 16
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