D ts e t
aa h e
R c e t r lc r nc
o h se Ee to is
Ma u a t r dCo o e t
n fc u e
mp n n s
R c e tr b a d d c mp n ns ae
o h se rn e
o oet r
ma ua trd u ig ete dewaes
n fcue sn i r i/ fr
h
p rh s d f m te oiia s p l r
uc a e r
o h r n l u pi s
g
e
o R c e tr waes rce td f m
r o h se
fr e rae r
o
te oiia I. Al rce t n ae
h
r nl P
g
l e rai s r
o
d n wi tea p o a o teOC
o e t h p rv l f h
h
M.
P r aetse u igoiia fcoy
at r e td sn r n la tr
s
g
ts p o rmso R c e tr e eo e
e t rga
r o h se d v lp d
ts s lt n t g aa te p o u t
e t oui s o u rne
o
rd c
me t o e c e teOC d t s e t
es r x e d h
M aa h e.
Qu l yOv riw
ai
t
e ve
• IO- 0 1
S 90
•A 92 cr ct n
S 1 0 et ai
i
o
• Qu l e Ma ua trr Ls (
ai d
n fcues it QML MI- R -
) LP F
385
53
•C a sQ Mitr
ls
lay
i
•C a sVS a eL v l
ls
p c ee
• Qu l e S p l r Ls o D sr uos( L )
ai d u pi s it f it b tr QS D
e
i
•R c e trsacic l u pir oD A a d
o h se i
r ia s p l t L n
t
e
me t aln u t a dD A sa d r s
es lid sr n L tn ad .
y
R c e tr lcrnc , L i c mmi e t
o h se Ee t is L C s o
o
tdo
t
s p ligp o u t ta s t f c so r x e t-
u pyn rd cs h t ai y u tme e p ca
s
t n fr u lya daee u loto eoiial
i s o q ai n r q a t h s r n l
o
t
g
y
s p l db id sr ma ua trr.
u pi
e yn ut
y n fcues
T eoiia ma ua trr d ts e t c o a yn ti d c me t e e t tep r r n e
h r n l n fcue’ aa h e a c mp n ig hs o u n r cs h ef ma c
g
s
o
a ds e ic t n o teR c e tr n fcue v rino ti d vc . o h se Ee t n
n p c ai s f h o h se ma ua trd eso f hs e ie R c e tr lcr -
o
o
isg aa te tep r r n eo i s mio d co p o u t t teoiia OE s e ic -
c u rne s h ef ma c ft e c n u tr rd cs o h r n l M p c a
o
s
g
t n .T pc lv le aefr eee c p r o e o l. eti mii m o ma i m rt g
i s ‘y ia’ au s r o rfrn e up s s ny C r n nmu
o
a
r xmu ai s
n
ma b b s do p o u t h rceiain d sg , i lt n o s mpetsig
y e a e n rd c c aa tr t , e in smuai , r a l e t .
z o
o
n
© 2 1 R cetr l t n s LC Al i t R sre 0 1 2 1
0 3 ohs E cr i , L . lRg s eevd 7 1 0 3
e e oc
h
T l r m r, l s v iw wrcl . m
o e n oe p ae it w . e c o
a
e
s
o ec
NCP4330
Post Regulation Driver
The NCP4330 houses a dual MOSFET driver intended to be used as
a companion chip in AC−DC or DC−DC multi−output post regulated
power supplies. Being directly fed by the secondary AC signal, the
device keeps power dissipation to the lowest while reducing the
surrounding part count. Furthermore, the implementation of a
N−channel MOSFET gives NCP4330−based applications a significant
advantage in terms of efficiency.
Features
http://onsemi.com
MARKING
DIAGRAM
8
8
1
SO−8
D SUFFIX
CASE 751
4330D
ALYW
G
•
•
•
•
•
•
•
•
•
Undervoltage Lockout
Thermal Shutdown for Overtemperature Protection
PWM Operation Synchronized to the Converter Frequency
High Gate Drive Capability
Bootstrap for N−MOSFET High−Side Drive
Over−Lap Management for Soft Switching
High Efficiency Post−Regulation
Ideal for Frequencies up to 400 kHz
This is a Pb−Free Device
1
4330D = Device Number
A
= Assembly Location
L
= Wafer Lot
Y
= Year
W
= Work Week
G
= Pb−Free Package
Typical Applications
•
ATX 3V3 Post−Regulation
•
Offline SMPS with MAGAMP Post−Regulation
•
Multi−Outputs DC−DC Converters
V
DD
V
DD
V
DD
Undervoltage Detection
(UVD high if V
DD
< 4.9 V)
RST
Vref, UVDth
Band−Gap
Level
Shifter
AR2
HS_DRV
Buffer
PIN CONNECTIONS
HS_DRV 1
BST 2
BST
RST 3
C_ramp 4
(Top View)
8 GND
7 LS_DRV
6 V
DD
5 I_ramp
UVD
HS_DRV and
LS_DRV low
RESET Block
2.5 V/1.5 V
U4
+
-
V
DD
Current
Mirror
OR
Hysteresis
Comparator
U3
U1
INVERTER
ORDERING INFORMATION
Device
NCP4330DR2G
V
DD
Package
SO−8
(Pb−Free)
Shipping
†
2500 / Tape & Reel
C_ramp
I_ramp
Iramp
Iramp
AR3
Buffer
†For information on tape and reel specifications,
including part orientation and tape sizes, please
refer to our Tape and Reel Packaging Specification
Brochure, BRD8011/D.
LS_DRV
GND
Figure 1. Block Diagram
©
Semiconductor Components Industries, LLC, 2011
April, 2011
−
Rev. 1
1
Publication Order Number:
NCP4330/D
NCP4330
Converter Winding
Voltage
0V
Time
Synchronization
Signal
2.55 V
Time
Internal RESET
Signal
C_ramp Voltage
0V
VrefH
VrefL
Time
Time
High−Side Driver
(referenced to
HS MOSFET source)
Time
Low−Side Driver
100 ns delay
100 ns delay
Time
Figure 2. Timing Diagram(s)
DETAILED PIN DESCRIPTION(S)
Pin
Number
1
2
Name
HS_DRV
BST
Function
“HS_DRV” is the gate driver of the high−side MOSFET.
“BST” is the bootstrap pin. A 0.1
mF
to 1.0
mF
ceramic capacitor should be connected between this pin
and the node that is common to the coil and the two MOSFET. The “BST” voltage feeds the high−side
driver (“HS_DRV”).
The “RST” pin resets the C_ramp voltage in order to synchronize the post−regulator free−wheeling
sequence to the forward converter demagnetization phase.
The capacitor connected to the C_ramp pin enables to adjust the delay in turning on the high−side
MOSFET (in conjunction with “I_ramp” current).
The “I_ramp” pin receives a current supplied by a regulation means. This current adjusts the delay after
which the high−side MOSFET is turned on. By this way, it modules the high−side MOSFET on time in
order to regulate the output voltage.
“V
DD
” is the power supply input. A 0.1
mF
to 1.0
mF
ceramic capacitor should be connected from this pin
to ground for decoupling.
“LS_DRV” is the driver output of the low−side MOSFET gate.
Ground.
3
4
5
RST
C_ramp
I_ramp
6
7
8
V
DD
LS_DRV
GND
http://onsemi.com
2
NCP4330
MAXIMUM RATINGS
Symbol
BST
RST
C_ramp
I_ramp
V
DD
R
qJA
T
J
T
Jmax
T
Smax
T
Lmax
Bootstrap Input
Reset Input
Timing Capacitor Node (Note 1)
Regulation Current Input (Note 1)
Supply Voltage
Thermal Resistance
Operating Junction Temperature Range (Note 2)
Maximum Junction Temperature
Storage Temperature Range
Lead Temperature (Soldering, 10 s)
Rating
Value
−0.3,
+40
−0.3,
+5.0
−0.3,
V
rampHL
−0.3,
Vcl
−0.3,
+20
180
−40,
+125
150
−65
to +150
300
Unit
V
V
V
V
V
°C/W
°C
°C
°C
°C
Stresses exceeding Maximum Ratings may damage the device. Maximum Ratings are stress ratings only. Functional operation above the
Recommended Operating Conditions is not implied. Extended exposure to stresses above the Recommended Operating Conditions may affect
device reliability.
1. V
rampHL
and Vcl are the internal clamp levels of pins 4 and 5 respectively.
2. The maximum junction temperature should not be exceeded.
ELECTRICAL CHARACTERISTICS
(V
DD
= 10 V, V
BST
= 25 V, T
J
from
−25°C
to +125°C, unless otherwise specified.)
Symbol
High−Side Output Stage
V
HS_H
V
HS_L
I
source_HS
I
sink_HS
t
r−HS
t
f−HS
T
LS−HS
V
LS_H
V
LS_L
I
source_LS
I
sink_LS
t
r−LS
t
f−LS
I
charge
High−Side Output Voltage in High State @ Isource =
−100
mA
High−Side Output Voltage in Low State @ Isink = 100 mA
Current Capability of the High−Side Drive Output in High State
Current Capability of the High−Side Drive Output in Low State
High−Side Output Voltage Rise Time from 0.5 V to 12 V (C
L
= 1.0 nF)
High−Side Output Voltage Fall Time from 20 V to 0.5 V (C
L
= 1.0 nF)
Delay from Low−Side Gate Drive Low (High) to High−Side Drive High (Low)
22.5
−
−
−
−
−
−
23.5
0.9
0.5
0.75
25
25
100
−
1.5
−
−
−
−
−
V
V
A
A
ns
ns
ns
Characteristic
Min
Typ
Max
Unit
Low−Side Output Stage
Low−Side Output Voltage in High State @ Isource =
−500
mA
Low−Side Output Voltage in Low State @ Isink = 750 mA
Current Capability of the Low−Side Drive Output in High State
Current Capability of the Low−Side Drive Output in Low State
Low−Side Output Voltage Rise Time from 0.5 V to 7.0 V (C
L
= 2.0 nF)
Low−Side Output Voltage Fall Time from 9.5 V to 0.5 V (C
L
= 2.0 nF)
C_ramp Current
@ Ipin5 = 100
mA
@ Ipin5 = 1.5 mA
Pin5 Clamp Voltage @ Ipin5 = 1.5 mA
Ramp Control Reference Voltage, Vpin4 Falling
Ramp Control Reference Voltage, Vpin4 Rising
Ramp Voltage Maximum Value @ Ipin5 = 1.5 mA
Ramp Voltage Low Voltage @ Ipin5 = 1.5 mA
7.4
−
−
−
−
−
8.2
1.3
0.5
0.75
25
25
−
1.7
−
−
−
−
V
V
A
A
ns
ns
Ramp Control
90
1400
0.7
1.3
2.25
3.2
−
102
1590
1.4
1. 5
2.5
3.6
−
110
1800
2.1
1.7
2.75
4.2
100
mA
Vcl
Vref
L
Vref
H
V
rampHL
V
rampLL
V
V
V
V
mV
http://onsemi.com
3
NCP4330
ELECTRICAL CHARACTERISTICS (continued)
(V
DD
= 10 V, V
BST
= 25 V, T
J
from
−25°C
to +125°C, unless otherwise
specified.)
Symbol
V
DD
Management
UVD
H
UVD
L
H
UVD
I
DD1
I
DD2
I
DD3
Reset Block
V
rst_th
H
rst
T
reset
I
reset
V
cl−neg
BST Leakage
BST
leakage
BST Leakage Current
(BST = 10 V, V
DD
= 1.5 V, other pins grounded, T
J
= 25°C)
−
8.0
15
mA
Reset Block Threshold
Reset Comparator Hysteresis
Reset Pulse Duration
C_ramp Pin Average Current, a 200 kHz, 50% duty cycle Pulse Generator
being applied to reset pin and 1.0 V to pin 4 (C_ramp) and @ Iramp = 0
Negative Clamp Level @ Ipin3 =
−2.0
mA
2.2
0.8
−
0.3
−0.5
2.5
1.0
250
0.7
−0.3
2.8
−
500
−
0
V
V
ns
mA
V
Undervoltage Lockout Threshold (V
DD
Rising)
Undervoltage Lockout Threshold (V
DD
Falling)
Undervoltage Lockout Hysteresis
Consumption:
@ Vpin4 = 3.0 V and Ipin5 = 500
mA
@ Vpin4 = 0 V and Ipin5 = 500
mA
@ Vpin4 Oscillating 0 to 3.0 V at 200 kHz, Ipin5 = 500
mA
5.2
4.9
400
−
−
−
5.8
5.2
600
13
7.0
10
6.4
5.5
−
20
12
15
V
V
mV
mA
Characteristic
Min
Typ
Max
Unit
Temperature Protection
T
limit
H
temp
Thermal Shutdown Threshold
Thermal Shutdown Hysteresis
−
−
150
50
−
−
°C
°C
http://onsemi.com
4
京公网安备 11010802033920号
EEWORLD
