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ASM3P623S00EG-16-SR

Description
3P SERIES, PLL BASED CLOCK DRIVER, 8 TRUE OUTPUT(S), 0 INVERTED OUTPUT(S), PDSO16, 0.150 INCH, GREEN, SOIC-16
Categorylogic    logic   
File Size544KB,15 Pages
ManufacturerON Semiconductor
Websitehttp://www.onsemi.cn
Download Datasheet Parametric View All

ASM3P623S00EG-16-SR Overview

3P SERIES, PLL BASED CLOCK DRIVER, 8 TRUE OUTPUT(S), 0 INVERTED OUTPUT(S), PDSO16, 0.150 INCH, GREEN, SOIC-16

ASM3P623S00EG-16-SR Parametric

Parameter NameAttribute value
MakerON Semiconductor
Parts packaging codeSOIC
package instructionSOP,
Contacts16
Reach Compliance Codeunknown
series3P
Input adjustmentSTANDARD
JESD-30 codeR-PDSO-G16
length9.905 mm
Logic integrated circuit typePLL BASED CLOCK DRIVER
Number of functions1
Number of inverted outputs
Number of terminals16
Actual output times8
Maximum operating temperature85 °C
Minimum operating temperature-40 °C
Package body materialPLASTIC/EPOXY
encapsulated codeSOP
Package shapeRECTANGULAR
Package formSMALL OUTLINE
Peak Reflow Temperature (Celsius)NOT SPECIFIED
propagation delay (tpd)0.35 ns
Certification statusNot Qualified
Same Edge Skew-Max(tskwd)0.25 ns
Maximum seat height1.75 mm
Maximum supply voltage (Vsup)3.6 V
Minimum supply voltage (Vsup)3 V
Nominal supply voltage (Vsup)3.3 V
surface mountYES
technologyCMOS
Temperature levelINDUSTRIAL
Terminal formGULL WING
Terminal pitch1.27 mm
Terminal locationDUAL
Maximum time at peak reflow temperatureNOT SPECIFIED
width3.9 mm
minfmax50 MHz
May 2008
rev 0.5
Timing-Safe™ Peak EMI reduction IC
ASM3P623S00B/E
General Features
Clock distribution with Timing-Safe™ Peak EMI
Reduction
Input frequency range: 20MHz - 50MHz
2 different Spread Selection option
Spread Spectrum can be turned ON/OFF
External Input-Output Delay Control option
Supply Voltage: 3.3V±0.3V
Commercial and Industrial temperature range
Packaging Information:
ASM3P623S00B: 8 pin SOIC, and TSSOP
ASM3P623S00E:16 pin SOIC, and TSSOP
The First True Drop-in Solution
Safe™ clock. ASM3P623S00E accepts one reference input
and drives out eight low-skew Timing-Safe™clocks.
ASM3P623S00B/E has an SS% that selects 2 different
Deviation and associated Input-Output Skew (T
SKEW
). Refer
Spread Spectrum Control and Input-Output Skew
table
for details.
ASM3P623S00E has a CLKOUT for adjusting the Input-
Output clock delay, depending upon the value of capacitor
connected at this pin to GND.
ASM3P623S00B/E operates from a 3.3V supply and is
available in two different packages, as shown in the
ordering information table, over commercial and Industrial
temperature range.
Functional Description
Application
ASM3P623S00B/E is a versatile, 3.3V Zero-delay buffer
designed to distribute Timing-Safe™ clocks with Peak EMI
reduction. ASM3P623S00B is an eight-pin version, accepts
one reference input and drives out one low-skew Timing-
ASM3P623S00B/E is targeted for use in Displays and
memory interface systems.
General Block Diagram
DLY_CTRL
VDD
SS%
CLKIN
PLL
CLKOUT(s)*
(Timing-Safe™)
*For
ASM3P623S00E -
8 CLKOUTS
SSON
GND
PulseCore Semiconductor Corporation
1715 S. Bascom Ave Suite 200 Campbell, CA 95008
Tel: 408-879-9077
Fax: 408-879-9018
www.pulsecoresemi.com
Notice: The information in this document is subject to change without notice.
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