CY7C376-83GC datasheet, PDF - EEWORLD Datasheet

CY7C376-83GC: DescriptionFlash PLD, 15ns, CMOS, CPGA160, CERAMIC, PGA-160; CategoryProgrammable logic devices Programmable logic; File Size38KB，1 Pages; ManufacturerCypress Semiconductor

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CY7C376-83GC Overview

Flash PLD, 15ns, CMOS, CPGA160, CERAMIC, PGA-160

Parameter Name	Attribute value
Maker	Cypress Semiconductor
Parts packaging code	PGA
package instruction	PGA,
Contacts	160
Reach Compliance Code	unknown
Other features	LABS INTERCONNECTED BY PIA; 12 LABS; 192 MACROCELLS; 4 EXTERNAL CLOCKS
maximum clock frequency	83 MHz
JESD-30 code	S-CPGA-P160
JESD-609 code	e0
length	39.751 mm
Dedicated input times	2
Number of I/O lines	128
Number of terminals	160
Maximum operating temperature	70 °C
Minimum operating temperature
organize	2 DEDICATED INPUTS, 128 I/O
Output function	MACROCELL
Package body material	CERAMIC, METAL-SEALED COFIRED
encapsulated code	PGA
Package shape	SQUARE
Package form	GRID ARRAY
Programmable logic type	FLASH PLD
propagation delay	15 ns
Certification status	Not Qualified
Maximum seat height	5.207 mm
Nominal supply voltage	5 V
surface mount	NO
technology	CMOS
Temperature level	COMMERCIAL
Terminal surface	TIN LEAD
Terminal form	PIN/PEG
Terminal pitch	2.54 mm
Terminal location	PERPENDICULAR
width	39.751 mm

	CY7C376-83GC	CY7C376-83AC
Description	Flash PLD, 15ns, CMOS, CPGA160, CERAMIC, PGA-160	Flash PLD, 15ns, CMOS, PQFP160, TQFP-160
Maker	Cypress Semiconductor	Cypress Semiconductor
Parts packaging code	PGA	QFP
package instruction	PGA,	LFQFP,
Contacts	160	160
Reach Compliance Code	unknown	unknown
Other features	LABS INTERCONNECTED BY PIA; 12 LABS; 192 MACROCELLS; 4 EXTERNAL CLOCKS	LABS INTERCONNECTED BY PIA; 12 LABS; 192 MACROCELLS; 4 EXTERNAL CLOCKS
maximum clock frequency	83 MHz	83 MHz
JESD-30 code	S-CPGA-P160	S-PQFP-G160
JESD-609 code	e0	e0
length	39.751 mm	24 mm
Dedicated input times	2	2
Number of I/O lines	128	128
Number of terminals	160	160
Maximum operating temperature	70 °C	70 °C
organize	2 DEDICATED INPUTS, 128 I/O	2 DEDICATED INPUTS, 128 I/O
Output function	MACROCELL	MACROCELL
Package body material	CERAMIC, METAL-SEALED COFIRED	PLASTIC/EPOXY
encapsulated code	PGA	LFQFP
Package shape	SQUARE	SQUARE
Package form	GRID ARRAY	FLATPACK, LOW PROFILE, FINE PITCH
Programmable logic type	FLASH PLD	FLASH PLD
propagation delay	15 ns	15 ns
Certification status	Not Qualified	Not Qualified
Maximum seat height	5.207 mm	1.6 mm
Nominal supply voltage	5 V	5 V
surface mount	NO	YES
technology	CMOS	CMOS
Temperature level	COMMERCIAL	COMMERCIAL
Terminal surface	TIN LEAD	TIN LEAD
Terminal form	PIN/PEG	GULL WING
Terminal pitch	2.54 mm	0.5 mm
Terminal location	PERPENDICULAR	QUAD
width	39.751 mm	24 mm

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