MACH 4 CPLD Family
High Performance EE CMOS
Programmable Logic
FEATURES
x
High-performance, EE CMOS 3.3-V & 5-V CPLD families
x
Flexible architecture for rapid logic designs
I
MAC ncludes
H 4A
Adv
Fa
M4A
ance
Info mily
-32/
Prel 32 and
rmatio
imin
M4A
n
ary
Infor
-128
mati /64
on
x
x
x
x
x
x
x
x
— Excellent First-Time-Fit
TM
and refit feature
— SpeedLocking
TM
performance for guaranteed fixed timing
— Central, input and output switch matrices for 100% routability and 100% pin-out retention
High speed
— 5.0ns t
PD
Commercial and 7.5ns t
PD
Industrial
— 182MHz f
CNT
32 to 512 macrocells; 32 to 768 registers
44 to 352 pins in PLCC, PQFP, TQFP, BGA, fpBGA or caBGA packages
Flexible architecture for a wide range of design styles
— D/T registers and latches
— Synchronous or asynchronous mode
— Dedicated input registers
— Programmable polarity
— Reset/ preset swapping
Advanced capabilities for easy system integration
— 3.3-V & 5-V JEDEC-compliant operations
— JTAG (IEEE 1149.1) compliant for boundary scan testing
— 3.3-V & 5-V JTAG in-system programming
— PCI compliant (-5/-55/-65/-7/-10/-12 speed grades)
— Safe for mixed supply voltage system designs
— Programmable pull-up or Bus-Friendly
TM
inputs and I/Os
— Hot-socketing
— Programmable security bit
— Individual output slew rate control
Advanced EE CMOS process provides high-performance, cost-effective solutions
Supported by ispDesignEXPERT
TM
software for rapid logic development
— Supports HDL design methodologies with results optimized for MACH 4A
— Flexibility to adapt to user requirements
— Software partnerships that ensure customer success
Lattice/Vantis and third-party hardware programming support
— Lattice/VantisPRO
TM
(formerly known as MACHPRO
®
) software for in-system programmability
support on PCs and automated test equipment
— Programming support on all major programmers including Data I/O, BP Microsystems, Advin,
and System General
Publication#
17466
Amendment/0
Rev:
K
Issue Date:
January 2000
Table 1. MACH 4 Device Features
1,2
Feature
Macrocells
Maximum User I/O Pins
t
PD
(ns)
f
CNT
(MHz)
t
COS
(ns)
t
SS
(ns)
Static Power (mA)
JTAG Compliant
PCI Compliant
M4-32/32
M4LV-32/32
32
32
7.5
111
5.5
5.5
25
Yes
Yes
M4-64/32
M4LV-64/32
64
32
7.5
111
5.5
5.5
25
Yes
Yes
M4-96/48
M4LV-96/48
96
48
7.5
111
5.5
5.5
50
Yes
Yes
M4-128/64
M4LV-128/64
128
64
7.5
111
5.5
5.5
70
Yes
Yes
M4-128N/64
M4LV-128N/64
128
64
7.5
111
5.5
5.5
70
No
Yes
M4-192/96
M4LV-192/96
192
96
7.5
111
5.5
5.5
85
Yes
Yes
M4-256/128
M4LV-256/128
256
128
7.5
111
5.5
5.5
100
Yes
Yes
Notes:
1. For information on the M4-96/96 device, please refer to the M4-96/96 datasheet at www.latticesemi.com.
2. “M4-xxx” is for 5-V devices. “M4LV-xxx” is for 3.3-V devices.
2
MACH 4 Family
Table 2. MACH 4A Device Features
3.3 V Devices
Feature
Macrocells
User I/O options
t
PD
(ns)
f
CNT
(MHz)
t
COS
(ns)
t
SS
(ns)
Static Power (mA)
JTAG Compliant
PCI Compliant
5 V Devices
Feature
Macrocells
User I/O options
t
PD
(ns)
f
CNT
(MHz)
t
COS
(ns)
t
SS
(ns)
Static Power (mA)
JTAG Compliant
PCI Compliant
M4A5-32
2
32
32
5.0
182
4.0
3.0
20
Yes
Yes
M4A5-64
1
64
32
5.5
167
4.0
3.5
TBD
Yes
Yes
M4A5-96
1
96
48
5.5
167
4.0
3.5
TBD
Yes
Yes
M4A5-128
2
128
64
5.5
167
4.0
3.5
55
Yes
Yes
M4A5-192
1
192
96
6.5
154
4.5
4.0
TBD
Yes
Yes
M4A5-256
1
256
128
6.5
154
4.5
4.0
TBD
Yes
Yes
M4A3-32
2
32
32
5.0
182
4.0
3.0
20
Yes
Yes
M4A3-64
1
64
32
5.5
167
4.0
3.5
TBD
Yes
Yes
M4A3-96
1
96
48
5.5
167
4.0
3.5
TBD
Yes
Yes
M4A3-128
2
128
64
5.5
167
4.0
3.5
55
Yes
Yes
M4A3-192
1
192
96
6.5
154
4.5
4.0
TBD
Yes
Yes
M4A3-256
1
256
128/160/192
6.5
154
4.5
4.0
TBD
Yes
Yes
M4A3-384
1
384
132/160/192
7.5
125
5.0
5.5
TBD
Yes
Yes
M4A3-512
1
512
132/160/192/
256
7.5
125
5.0
5.5
TBD
Yes
Yes
Notes:
1. Advance information is shaded. Please contact a Lattice/Vantis sales representative for details on availability.
2. Preliminary information.
MACH 4 Family
3
GENERAL DESCRIPTION
The MACH
®
4 family from Lattice/Vantis offers an exceptionally flexible architecture and delivers
a superior Complex Programmable Logic Device (CPLD) solution of easy-to-use silicon products
and software tools. The overall benefits for users are a guaranteed and predictable CPLD
solution, faster time-to-market, greater flexibility and lower cost. The MACH 4 devices offer
densities ranging from 32 to 512 macrocells with 100% utilization and 100% pin-out retention.
Both the MACH 4 and the MACH 4A families offer 5-V (M4-xxx and M4A5-xxx) and 3.3-V (M4LV-
xxx and M4A3-xxx) operation.
MACH 4 products are 5-V or 3.3-V in-system programmable through the JTAG (IEEE Std. 1149.1)
interface. JTAG boundary scan testing also allows product testability on automated test
equipment for device connectivity.
All MACH 4 family members deliver First-Time-Fit and easy system integration with pin-out
retention after any design change and refit. For both 3.3-V and 5-V operation, MACH 4 products
can deliver guaranteed fixed timing as fast as 5.0 ns t
PD
and 182 MHz f
CNT
through the
SpeedLocking feature when using up to 20 product terms per output (Tables 3 and 4).
Table 3. MACH 4 Speed Grades
Speed Grade
1
Device
M4-32/32
M4LV-32/32
M4-64/32
M4LV-64/32
M4-96/48
M4LV-96/48
M4-128/64
M4LV-128/64
M4-128N/64
M4LV-128N/64
M4-192/96
M4LV-192/96
M4-256/128
M4LV-256/128
Note:
1. C = Commercial,
-7
C
C
C
C
C
C
C
-10
C, I
C, I
C, I
C, I
C, I
C, I
C, I
-12
C, I
C, I
C, I
C, I
C, I
C, I
C, I
-14
I
I
I
I
I
I
I
-15
C
C
C
C
C
C
C
-18
I
I
I
I
I
I
I
I = Industrial
4
MACH 4 Family
Table 4. MACH 4A Speed Grades
Speed Grade
Device
M4A3-32
3
M4A5-32
3
M4A3-64
2
M4A5-64
2
M4A3-96
2
M4A5-96
2
M4A3-128
3
M4A5-128
3
M4A3-192
2
M4A5-192
2
M4A3-256
2
M4A5-256
2
M4A3-384
2
M4A3-512
2
Notes:
1. C = Commercial,
-5
C
C
C
C
C
C
-55
-65
-7
C, I
C, I
C, I
C, I
C
C
C
C
-10
C, I
C, I
C, I
C, I
C, I
C, I
C, I
C, I
-12
I
I
I
I
I
I
C, I
C, I
I
I
-14
I = Industrial
2. Advance information is shaded. Please contact a Lattice/Vantis sales representative for details on availability.
3. Preliminary information.
The MACH 4 family offers 20 density-I/O combinations in Thin Quad Flat Pack (TQFP), Plastic
Quad Flat Pack (PQFP), Plastic Leaded Chip Carrier (PLCC), Ball Grid Array (BGA), fine-pitch
BGA (fpBGA), and chip-array BGA (caBGA) packages ranging from 44 to 352 pins (Tables 5 and
6). It also offers I/O safety features for mixed-voltage designs so that the 3.3-V devices can accept
5-V inputs, and 5-V devices do not overdrive 3.3-V inputs. Additional features include Bus-
Friendly inputs and I/Os, a programmable power-down mode for extra power savings and
individual output slew rate control for the highest speed transition or for the lowest noise
transition.
Table 5. MACH 4 Package and I/O Options (Number of I/Os and dedicated inputs in Table)
Package
44-pin PLCC
44-pin TQFP
48-pin TQFP
84-pin PLCC
100-pin TQFP
100-pin PQFP
144-pin TQFP
208-pin PQFP
256-ball BGA
48+8
64+6
64+6
96+16
128+14
128+14
M4-32/32
M4LV-32/32
32+2
32+2
32+2
M4-64/32
M4LV-64/32
32+2
32+2
32+2
64+6
M4-96/48
M4LV-96/48
M4-128/64
M4LV-128/64
M4-128N/64
M4LV-128N/64
M4-192/96
M4LV-192/96
M4-256/128
M4LV-256/128
MACH 4 Family
5
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