clock inputs and provides nine outputs partitioned in four
banks of 1, 1, 2, and 5 outputs. Bank A divides the VCO
output by 2 or 4 while the other banks divide by 4 or 8 per
SEL(A:D) settings, see Table 2. These dividers allow
output to input ratios of 16:1, 8:1, 4:1, and 2:1. Each
LVCMOS compatible output can drive 50Ω series or
parallel
terminated
transmission
lines.
For
series
terminated transmission lines, each output can drive one or
two traces giving the device an effective fanout of 1:18.
The PLL is ensured stable given that the VCO is configured
to run between 200MHz to 500MHz. This allows a wide
range of output frequencies from 25MHz to 200MHz. The
internal VCO is running at multiples of the input reference
clock set by the feedback divider, see Table 1.
When PLL_EN is LOW, PLL is bypassed and the reference
clock directly feeds the output dividers. This mode is fully
static and the minimum input clock frequency specification
Functional Description
The
ASM5I9350
is
a
low-voltage
high-performance
does not apply.
200MHz PLL-based clock driver designed for high speed
clock distribution applications.
Alliance Semiconductor
2575, Augustine Drive
•
Santa Clara, CA
•
Tel: 408.855.4900
•
Fax: 408.855.4999
•
www.alsc.com
Notice: The information in this document is subject to change without notice.
July 2005
rev 0.2
Block Diagram
ASM5I9350
SELA
PLL_EN
REF_SEL
TCLK
XIN
XOUT
osc
Phase
Detector
VCO
200-500MHz
LPF
+2/
+4
QA
+16/+32
FB_SEL
SELB
+4/
+8
QB
QC0
QC1
QD0
QD1
QD2
QD3
QD4
+4/
+8
SELC
+4/
+8
SELD
OE#
REF_SEL
PLL_EN
VSS
VDDQB
Pin Configuration
TCLK
32 31 30 29 28 27 26 25
AVDD
FB_SEL
SELA
SELB
SELC
SELD
AVSS
XOUT
1
2
3
4
5
6
7
8
9 10 11 12 13 14 15 16
24
23
22
QC0
VDDQC
QC1
VSS
QD0
VDDQD
QD1
VSS
ASM5I9350
VSS
21
20
19
18
17
QD2
QA
XIN
VDD
3.3V 1:10 LVCMOS PLL Clock Generator
Notice: The information in this document is subject to change without notice.
VDDQD
VSS
OE#
QD4
QD3
QB
2 of 12
July 2005
rev 0.2
Pin Discription
1
Pin #
8
9
30
28
26
22, 24
12, 14, 16,
18, 20
2
10
31
32
3, 4, 5, 6
27
23
15, 19
1
11
7
13, 17, 21,
25, 29
ASM5I9350
Pin Name
XOUT
XIN
TCLK
QA
QB
QC(1:0)
QD(4:0)
FB_SEL
OE#
PLL_EN
REF_SEL
SEL(A:D)
VDDQB
VDDQC
VDDQD
AVDD
VDD
AVSS
VSS
I/O
O
I
I, PD
O
O
O
O
I, PD
I, PD
I, PU
I, PD
I, PD
Supply
Supply
Supply
Supply
Supply
Supply
Supply
Type
Analog
Analog
LVCMOS
LVCMOS
LVCMOS
LVCMOS
LVCMOS
LVCMOS
LVCMOS
LVCMOS
LVCMOS
LVCMOS
VDD
VDD
VDD
VDD
VDD
Ground
Ground
Description
Oscillator Output.
Connect to a crystal.
Oscillator Input.
Connect to a crystal.
LVCMOS/LVTTL reference clock input
Clock output bank A
Clock output bank B
Clock output bank C
Clock output bank D
Internal Feedback Select Input.
See
Table 1.
Output enable/disable input.
See
Table 2.
PLL enable/disable input.
See
Table 2.
Reference select input.
See
Table 2.
Frequency select input, Bank (A:D).
See
Table 2.
2.5V or 3.3V Power supply for bank B output clock
2,3
2.5V or 3.3V Power supply for bank C output clocks
2,3
2.5V or 3.3V Power supply for bank D output clocks
2,3
2.5V or 3.3V Power supply for PLL
2,3
2.5V or 3.3V Power supply for core, inputs, and bank A
2,3
output clock
Analog ground
Common ground
Note: 1. PU = Internal pull-up, PD = Internal pull-down.
2. A 0.1µF bypass capacitor should be placed as close as possible to each positive power pin (<0.2”). If these bypass capacitors are not close to the pins
their high frequency filtering characteristics will be cancelled by the lead inductance of the traces.
3. AVDD and VDD pins must be connected to a power supply level that is at least equal or higher than that of VDDQB, VDDQC, and VDDQD output
power supply pins.
Table 1: Frequency Table
FB_SEL
0
1
Feedback Divider
÷32
÷16
VCO
Input Clock * 32
Input Clock * 16
Input Frequency
Range (AVDD = 3.3V)
6.25 MHz to 15.625 MHz
12.5 MHz to 31.25 MHz
Input Frequency
Range (AVDD = 2.5V)
6.25 MHz to 11.875 MHz
12.5 MHz to 23.75 MHz
3.3V 1:10 LVCMOS PLL Clock Generator
Notice: The information in this document is subject to change without notice.
3 of 12
July 2005
rev 0.2
Table 2: Function Table
Control
REF_SEL
PLL_EN
OE#
FB_SEL
SELA
SELB
SELC
SELD
ASM5I9350
Default
0
1
0
0
0
0
0
0
0
Xtal
Bypass mode, PLL disabled. The
input clock connects to the output
dividers
Outputs enabled
Feedback divider ÷32
÷2 (Bank A)
÷4 (Bank B)
÷4 (Bank C)
÷4 (Bank D)
1
TCLK
PLL enabled. The VCO output connects to
the output dividers
Outputs disabled (three-state)
Feedback divider ÷16
÷ 4 (Bank A)
÷ 8 (Bank B)
÷ 8 (Bank C)
÷ 8 (Bank D)
Absolute Maximum Ratings
Parameter
V
DD
V
DD
V
IN
V
OUT
V
TT
LU
R
PS
T
S
T
A
T
J
Ø
JC
Ø
JA
ESD
H
FIT
Description
DC Supply Voltage
DC Operating Voltage
DC Input Voltage
DC Output Voltage
Output termination Voltage
Latch Up Immunity
Power Supply Ripple
Temperature, Storage
Temperature, Operating Ambient
Temperature, Junction
Dissipation, Junction to Case
Dissipation, Junction to Ambient
ESD Protection (Human Body Model)
Failure in Time
Condition
Functional
Relative to V
SS
Relative to V
SS
Functional
Ripple Frequency < 100 kHz
Non-functional
Functional
Functional
Functional
Functional
Min
–0.3
2.375
–0.3
–0.3
200
Max
5.5
3.465
V
DD
+ 0.3
V
DD
+ 0.3
V
DD
÷2
150
Unit
V
V
V
V
V
mA
mVp-p
°C
°C
°C
°C/W
°C/W
Volts
ppm
–65
–40
+150
+85
+150
42
105
2000
Manufacturing test
10
3.3V 1:10 LVCMOS PLL Clock Generator
Notice: The information in this document is subject to change without notice.
4 of 12
July 2005
rev 0.2
DC Electrical Specifications
(V
CC
= 2.5V ± 5%, T
A
= -40°C to +85°C)
Parameter
V
IL
V
IH
V
OL
V
OH
I
IL
I
IH
I
DDA
I
DDQ
I
DD
C
IN
Z
OUT
ASM5I9350
Description
Input Voltage, Low
Input Voltage, High
Output Voltage, Low
Input Current, Low
2
1
1
Condition
LVCMOS
LVCMOS
I
OL
= 15mA
I
OH
= –15mA
V
IL
= V
SS
V
IL
= V
DD
AVDD only
All VDD pins except AVDD
Outputs loaded @ 100 MHz
Outputs loaded @ 200 MHz
Min
-
1.7
-
1.8
-
-
-
-
-
-
-
14
Typ
-
-
-
-
-
-
5
-
180
210
4
18
Max
0.7
V
DD
+0.3
0.6
-
-100
100
10
7
-
-
-
22
Unit
V
V
V
V
µA
µA
mA
mA
mA
pF
Ω
Output Voltage, High
Input Current, High
2
PLL Supply Current
Quiescent Supply Current
Dynamic Supply Current
Input Pin Capacitance
Output Impedance
Note: 1. Driving one 50Ω parallel terminated transmission line to a termination voltage of V
TT
. Alternatively, each output drives up to two 50Ω series terminated
transmission lines.
2. Inputs have pull-up or pull-down resistors that affect the input current.
DC Electrical Specifications
(V
CC
= 3.3V ± 5%, T
A
= -40°C to +85°C)
Parameter
V
IL
V
IH
V
OL
V
OH
I
IL
I
IH
I
DDA
I
DDQ
I
DD
C
IN
Z
OUT
Description
Input Voltage, Low
Input Voltage, High
Output Voltage, Low
1
Output Voltage, High
1
Input Current, Low
2
2
Condition
LVCMOS
LVCMOS
I
OL
= 24 mA
I
OL
= 12 mA
I
OH
= –24 mA
V
IL
= V
SS
V
IL
= V
DD
AVDD only
All VDD pins except AVDD
Outputs loaded @ 100 MHz
Outputs loaded @ 200 MHz
Min
-
2.0
-
-
2.4
-
-
-
-
-
-
-
12
Typ
-
-
-
-
-
-
-
5
-
270
300
4
15
Max
0.8
V
DD
+0.3
0.55
0.30
-
–100
100
10
7
-
-
-
18
Unit
V
V
V
V
µA
µA
mA
mA
mA
pF
Ω
Input Current, High
PLL Supply Current
Quiescent Supply Current
Dynamic Supply Current
Input Pin Capacitance
Output Impedance
Note: 1. Driving one 50Ω parallel terminated transmission line to a termination voltage of VTT. Alternatively, each output drives up to two 50Ω series terminated
transmission lines.
2. Inputs have pull-up or pull-down resistors that affect the input current.
3.3V 1:10 LVCMOS PLL Clock Generator
Notice: The information in this document is subject to change without notice.
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