reference clock while the ASM5I961P offers an LVPECL
reference clock.
When pulled high the OE pin will force all of the outputs
(except QFB) into a high impedance state. Because the OE
pin does not affect the QFB output, down stream clocks
can be disabled without the internal PLL losing lock.
The ASM5I961P is fully 2.5V or 3.3V compatible and
requires no external loop filter components. All control
inputs accept LVCMOS compatible levels and the outputs
provide low impedance LVCMOS outputs capable of
driving terminated 50Ω transmission lines. For series
terminated lines the ASM5I961P can drive two lines per
output giving the device an effective fanout of 1:36. The
device is packaged in a 32 lead LQFP package to provide
the
optimum
combination
of
board
density
and
performance.
Functional Description
The ASM5I961P is a 2.5V or 3.3V compatible, 1:18 PLL
based zero delay buffer. With output frequencies of up to
200MHz, output skews of 150pS the device meets the
needs of the most demanding clock tree applications.
The ASM5I961P is offered with two different input
configurations.
The ASM5I961P
offers an LVCMOS
Block Diagram
Figure 1. ASM5I961P Logic Diagram
Alliance Semiconductor
2575, Augustine Drive
•
Santa Clara, CA
•
Tel: 408.855.4900
•
Fax: 408.855.4999
•
www.alsc.com
Notice: The information in this document is subject to change without notice.
July 2005
rev 0.2
Pin Configuration
ASM5I961P
ASM5I961P
Figure 2. ASM5I961P 32-Lead Package Pinout
(Top View)
Table 1: Pin Configuration
Pin #
2,3
7
4
6
31,30,29,27,26,25,23,22,21
,19,18,17,15,14,13,11,10
9
1,12,20,28
Pin Name
PCLK, ¯¯¯¯¯
PCLK
FB_IN
F_RANGE
¯¯
OE
Q0 - Q16
QFB
GND
I/O
Input
Input
Input
Input
Output
Output
Supply
Type
LVCMOS
LVCMOS
LVCMOS
LVCMOS
LVCMOS
LVCMOS
Power
Function
PLL reference clock signal
PLL feedback signal input, connect to a QFB
output
PLL frequency range select
Output enable/disable
Clock outputs
PLL feedback signal output, connect to a
FB_IN
Negative power supply
PLL positive power supply (analog power
supply). The ASM5I961P requires an
external RC filter for the analog power
supply pin VCCA. Please see applications
section for details.
Positive power supply for I/O and core
5
VCCA
Supply
Power
8,16,24,32
VCC
Supply
Power
Low Voltage Zero Delay Buffer
Notice: The information in this document is subject to change without notice.
2 of 14
July 2005
rev 0.2
Table 2: Function Table
Control
F_RANGE
¯¯
OE
ASM5I961P
Default
0
0
0
PLL high frequency range. ASM5I961P input
reference and output clock frequency range is
100 – 200 MHz
Outputs enabled
1
PLL low frequency range. ASM5I961P input
reference and output clock frequency range is
50 – 100 MHz
Outputs disabled (high–impedance state)
Table 3: Absolute Maximum Ratings
Symbol
Parameter
V
CC
V
IN
V
OUT
I
IN
I
OUT
T
S
T
DV
Supply Voltage
DC Input Voltage
DC Output Voltage
DC Input Current
DC Output Current
Storage Temperature Range
Static Discharge Voltage
(As per JEDEC STD 22- A114-B)
Min
–0.3
–0.3
–0.3
Max
3.6
V
CC
+ 0.3
V
CC
+ 0.3
±20
±50
125
2
Unit
V
V
V
mA
mA
°C
KV
–40
Note: These are stress ratings only and are not implied for functional use. Exposure to absolute maximum ratings for prolonged periods of time may affect
device reliability.
Table 4: DC Characteristics
(V
CC
= 3.3V ± 5%, T
A
= -40°C to +85°C)
Symbol
V
IH
V
IL
V
PP
V
CMR
V
OH
V
OL
Z
OUT
I
IN
C
IN
C
PD
I
CCA
I
CC
V
TT
Characteristic
Input HIGH Voltage
Input LOW Voltage
Peak–to–peak input voltage
1
PECL_CLK,
¯¯¯¯¯¯¯¯¯¯
PECL_CLK
1
Common Mode Range
PECL_CLK,
¯¯¯¯¯¯¯¯¯¯
PECL_CLK
Output HIGH Voltage
Output LOW Voltage
Output Impedance
Input Current
Input Capacitance
Power Dissipation Capacitance
Maximum PLL Supply Current
Maximum Quiescent Supply Current
Output Termination Voltage
Min
2.0
–0.3
500
1.2
2.4
Typ
Max
V
CC
+ 0.3
0.8
1000
V
CC
– 0.8
0.55
Unit
V
V
mV
V
V
V
Ω
mA
pF
pF
mA
mA
V
Condition
LVCMOS
LVCMOS
LVPECL
LVPECL
I
OH
= –20mA
2
I
OL
= 20mA
2
14
4.0
8.0
2.0
V
CC
÷2
20
±120
10
5.0
Per Output
V
CCA
Pin
All V
CC
Pins
Notes:
1. Exceeding the specified V
CMR
/V
PP
window results in a t
PD
changes of approx. 250pS.
2. The ASM5I961P is capable of driving 50Ω transmission lines on the incident edge. Each output drives one 50Ω parallel terminated transmission line to a
termination voltage of V
TT
. Alternatively, the device drives up two 50Ω series terminated transmission lines.
Low Voltage Zero Delay Buffer
Notice: The information in this document is subject to change without notice.
3 of 14
July 2005
rev 0.2
Table 5: AC Characteristics
(V
CC
= 3.3V ± 5%, T
A
= -40°C to +85°C)
1
Symbol
f
ref
f
max
f
refDC
t
(
φ
)
t
sk(O)
DC
O
t
r
, t
f
t
PLZ,HZ
t
PZL,LZ
t
JIT(CC)
t
JIT(PER)
t
JIT(
φ
)
t
lock
ASM5I961P
Characteristic
Input Frequency
Maximum Output
Frequency
2
Min
100
50
100
50
25
–50
Typ
Max
200
100
200
100
75
225
Unit
MHz
MHz
%
pS
pS
%
nS
nS
nS
pS
pS
nS
mS
Condition
F_RANGE = 0
F_RANGE = 1
F_RANGE = 0
F_RANGE = 1
Reference Input Duty Cycle
PECL_CLK to
Propagation Delay
FB_IN
(static phase offset)
3
Output to Output Skew
F_RANGE = 0
Output Duty Cycle
F_RANGE = 1
Output Rise/Fall Time
Output Disable Time
Output Enable Time
Cycle to Cycle Jitter
Period Jitter
I/O Phase Jitter
Maximum PLL Lock Time
RMS (1σ)
4
PLL locked
90
42
45
0.1
50
50
150
55
55
1.0
10
10
15
0.55 to 2.4V
RMS (1σ)
RMS (1σ)
F_RANGE = 0
F_RANGE = 1
7.0
10
0.0015
⋅
T
0.0010
⋅
T
10
T = Clock
Signal
Period
Notes:
1. AC characteristics apply for parallel output termination of 50Ω to V
TT
.
2. t
PD
applies for V
CMR
= V
CC
–1.3V and V
PP
= 800mV
3. See applications section for part to part skew calculation
4. See applications section for calculation for other confidence factors than 1σ
Table 6: DC Characteristics
(V
CC
= 2.5V ± 5%, T
A
= –40° to 85°C)
Symbol
V
IH
V
IL
V
PP
V
CMR
V
OH
V
OL
Z
OUT
I
IN
C
IN
C
PD
I
CCA
I
CC
V
TT
Characteristic
Input HIGH Voltage
Input LOW Voltage
Peak–to–peak input voltage
1
PECL_CLK,
¯¯¯¯¯¯¯¯¯¯
PECL_CLK
1
Common Mode Range
PECL_CLK,
¯¯¯¯¯¯¯¯¯¯
PECL_CLK
Output HIGH Voltage
Output LOW Voltage
Output Impedance
Input Current
Input Capacitance
Power Dissipation Capacitance
Maximum PLL Supply Current
Maximum Quiescent Supply Current
Output Termination Voltage
Min
1.7
–0.3
500
1.2
1.8
Typ
Max
V
CC
+ 0.3
0.7
1000
V
CC
– 0.7
0.6
Unit
V
V
mV
V
V
V
Ω
mA
pF
pF
mA
mA
V
Condition
LVCMOS
LVCMOS
LVPECL
LVPECL
I
OH
= –15mA
2
I
OL
= 15mA
2
18
4.0
8.0
2.0
V
CC
÷2
26
±120
10
5.0
Per Output
V
CCA
Pin
All V
CC
Pins
Notes:
1. Exceeding the specified V
CMR
/V
PP
window results in a t
PD
changes of < 250 pS.
2. The ASM5I961P is capable of driving 50Ω transmission lines on the incident edge. Each output drives one 50Ω parallel terminated transmission line to a
termination voltage of V
TT
. Alternatively, the device drives up two 50Ω series terminated transmission lines.
Low Voltage Zero Delay Buffer
Notice: The information in this document is subject to change without notice.
4 of 14
July 2005
rev 0.2
Table 7: AC Characteristics
(V
CC
= 2.5V ± 5%, T
A
= -40°C to +85°C)
1
Symbol
f
ref
f
max
f
refDC
t
(
φ
)
t
sk(O)
DC
O
t
r
, t
f
t
PLZ,HZ
t
PZL,LZ
t
JIT(CC)
t
JIT(PER)
t
JIT(
φ
)
t
lock
ASM5I961P
Characteristic
Input Frequency
Maximum Output
Frequency
2
Min
100
50
100
50
25
–50
Typ
Max
200
100
200
100
75
175
Unit
MHz
MHz
%
pS
pS
%
nS
nS
nS
pS
pS
nS
mS
Condition
F_RANGE = 0
F_RANGE = 1
F_RANGE = 0
F_RANGE = 1
Reference Input Duty Cycle
PECL_CLK to
Propagation Delay
FB_IN
(static phase offset)
3
Output–to–Output Skew
F_RANGE = 0
Output Duty Cycle
F_RANGE = 1
Output Rise/Fall Time
Output Disable Time
Output Enable Time
Cycle–to–Cycle Jitter
Period Jitter
I/O Phase Jitter
Maximum PLL Lock Time
RMS (1σ)
4
RMS (1σ)
RMS (1σ)
F_RANGE = 0
F_RANGE = 1
PLL locked
90
40
45
0.1
50
50
150
60
55
1.0
10
10
15
0.6 to 1.8V
7.0
10
0.0015
⋅
T
0.0010
⋅
T
10
T = Clock
Signal
Period
Notes:
1. AC characteristics apply for parallel output termination of 50Ω to V
TT
.
2. t
PD
applies for V
CMR
= V
CC
–1.3V and V
PP
= 800mV
3. See applications section for part–to–part skew calculation
4. See applications section for calculation for other confidence factors than 1σ
Low Voltage Zero Delay Buffer
Notice: The information in this document is subject to change without notice.
京公网安备 11010802033920号
EEWORLD
