CD4051B, CD4052B, CD4053B
Semiconductor
August 1998
File Number 902.2
CMOS Analog Multiplexers/Demultiplexers
with Logic Level Conversion
The CD4051B, CD4052B, and CD4053B analog multiplexers
are digitally-controlled analog switches having low ON
impedance and very low OFF leakage current. Control of
analog signals up to 20V
P-P
can be achieved by digital
signal amplitudes of 4.5V to 20V (if V
DD
-V
SS
= 3V, a
V
DD
-V
EE
of up to 13V can be controlled; for V
DD
-V
DD
level differences above 13V, a V
DD
-V
DD
of at least 4.5V is
required). For example, if V
DD
= +4.5V, V
DD
= 0V, and
V
DD
= -13.5V, analog signals from -13.5V to +4.5V can be
controlled by digital inputs of 0V to 5V. These multiplexer
circuits dissipate extremely low quiescent power over the
full V
DD
-V
DD
and V
DD
-V
DD
supply-voltage ranges,
independent of the logic state of the control signals. When
a logic “1” is present at the inhibit input terminal, all
channels are off.
The CD4051B is a single 8-Channel multiplexer having three
binary control inputs, A, B, and C, and an inhibit input. The
three binary signals select 1 of 8 channels to be turned on,
and connect one of the 8 inputs to the output.
The CD4052B is a differential 4-Channel multiplexer having
two binary control inputs, A and B, and an inhibit input. The
two binary input signals select 1 of 4 pairs of channels to be
turned on and connect the analog inputs to the outputs.
The CD4053B is a triple 2-Channel multiplexer having three
separate digital control inputs, A, B, and C, and an inhibit
input. Each control input selects one of a pair of channels
which are connected in a single-pole, double-throw
configuration.
When these devices are used as demultiplexers, the
“CHANNEL IN/OUT” terminals are the outputs and the
“COMMON OUT/IN” terminals are the inputs.
Features
• Wide Range of Digital and Analog Signal Levels
- Digital . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3V to 20V
- Analog. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
≤20V
P-P
• Low ON Resistance, 125Ω (Typ) Over 15V
P-P
Signal Input
Range for V
DD
-V
EE
= 18V
• High OFF Resistance, Channel Leakage of
±100pA
(Typ)
at V
DD
-V
EE
= 18V
• Logic-Level Conversion for Digital Addressing Signals of
3V to 20V (V
DD
-V
SS
= 3V to 20V) to Switch Analog
Signals to 20V
P-P
(V
DD
-V
EE
= 20V)
• Matched Switch Characteristics, r
ON
= 5Ω (Typ) for
V
DD
-V
EE
= 15V
• Very Low Quiescent Power Dissipation Under All Digital-
Control Input and Supply Conditions, 0.2µW (Typ) at
V
DD
-V
SS
= V
DD
-V
EE
= 10V
• Binary Address Decoding on Chip
• 5V, 10V and 15V Parametric Ratings
• 10% Tested for Quiescent Current at 20V
• Maximum Input Current of 1µA at 18V Over Full Package
Temperature Range, 100nA at 18V and 25
o
C
• Break-Before-Make Switching Eliminates Channel
Overlap
Applications
• Analog and Digital Multiplexing and Demultiplexing
• A/D and D/A Conversion
• Signal Gating
Ordering Information
PART NUMBER
CD4051BF, CD4052BF,
CD4053BF
CD4051BE, CD4052BE,
CD4053BE
CD4051BM, CD4052BM,
CD4053BM
TEMP.
RANGE (
o
C)
-55 to 125
PACKAGE
PKG.
NO.
16 Ld CERDIP F16.3
-55 to 125
16 Ld PDIP
E16.3
-55 to 125
16 Ld SOIC
M16.15
1
CAUTION: These devices are sensitive to electrostatic discharge; follow proper IC Handling Procedures.
Copyright
©
Harris Corporation 1998
CD4051B, CD4052B, CD4053B
Absolute Maximum Ratings
Supply Voltage (V+ to V-)
Voltages Referenced to V
SS
Terminal . . . . . . . . . . . -0.5V to 20V
DC Input Voltage Range . . . . . . . . . . . . . . . . . . -0.5V to V
DD
+0.5V
DC Input Current, Any One Input. . . . . . . . . . . . . . . . . . . . . .
±10mA
Thermal Information
Thermal Resistance (Typical, Note 1)
θ
JA
(
o
C/W)
θ
JC
(
o
C/W)
PDIP Package . . . . . . . . . . . . . . . . . . .
90
N/A
CERDIP Package. . . . . . . . . . . . . . . . .
115
45
SOIC Package . . . . . . . . . . . . . . . . . . .
115
N/A
Maximum Junction Temperature (Ceramic Package) . . . . . . . . .175
o
C
Maximum Junction Temperature (Plastic Package) . . . . . . . .150
o
C
Maximum Storage Temperature Range . . . . . . . . . . -65
o
C to 150
o
C
Maximum Lead Temperature (Soldering 10s) . . . . . . . . . . . . .265
o
C
(SOIC - Lead Tips Only)
Operating Conditions
Temperature Range . . . . . . . . . . . . . . . . . . . . . . . . . -55
o
C to 125
o
C
CAUTION: Stresses above those listed in “Absolute Maximum Ratings” may cause permanent damage to the device. This is a stress only rating and operation of the
device at these or any other conditions above those indicated in the operational sections of this specification is not implied.
NOTE:
1.
θ
JA
is measured with the component mounted on an evaluation PC board in free air.
Electrical Specifications
Common Conditions Here: If Whole Table is For the Full Temp. Range, V
SUPPLY
=
±5V,
A
V
= +1,
R
L
= 100Ω, Unless Otherwise Specified (Note 3)
CONDITIONS
LIMITS AT INDICATED TEMPERATURES (
o
C)
25
PARAMETER
V
IS
(V)
V
EE
(V)
V
SS
(V)
V
DD
(V)
-55
-40
85
125
MIN
TYP
MAX
UNITS
SIGNAL INPUTS (V
IS
) AND OUTPUTS (V
OS
)
Quiescent Device
Current, I
DD
Max
-
-
-
-
Drain to Source ON
Resistance r
ON
Max
0
≤
V
IS
≤
V
DD
Change in ON
Resistance (Between
Any Two Channels),
∆r
ON
OFF Channel Leakage
Current: Any Channel
OFF (Max) or ALL
Channels OFF (Common
OUT/IN) (Max)
Capacitance:
Input, C
IS
Output, C
OS
CD4051
CD4052
CD4053
Feedthrough
C
IOS
Propagation Delay Time
(Signal Input to Output
V
DD
R
L
= 200kΩ,
C
L
= 50pF,
t
r
, t
f
= 20ns
5
10
15
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
0.2
30
15
10
-
60
30
20
pF
ns
ns
ns
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
30
18
9
-
-
-
pF
pF
pF
-
-
-
-
-
-
-
-
-
-
-
0
0
0
0
0
0
0
-
-
-
-
0
0
0
0
0
0
0
5
10
15
20
5
10
15
5
10
15
18
5
10
20
100
800
310
200
-
-
-
5
10
20
100
850
330
210
-
-
-
150
300
600
3000
1200
520
300
-
-
-
150
300
600
3000
1300
550
320
-
-
-
-
-
-
-
-
-
-
-
-
-
-
0.04
0.04
0.04
0.08
470
180
125
15
10
5
±0.01
5
10
20
100
1050
400
240
-
-
-
±100
(Note 2)
µA
µA
µA
µA
Ω
Ω
Ω
Ω
Ω
Ω
µA
±100
(Note 2)
±1000
(Note 2)
-
-5
5-
5
-
-
-
-
-
5
-
pF
5
Embedded System
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