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28C04AF-25/K

Description
512 X 8 EEPROM 5V, 250 ns, CQCC32, CERAMIC, LCC-32
Categorystorage    storage   
File Size59KB,8 Pages
ManufacturerMicrochip
Websitehttps://www.microchip.com
Download Datasheet Parametric View All

28C04AF-25/K Overview

512 X 8 EEPROM 5V, 250 ns, CQCC32, CERAMIC, LCC-32

28C04AF-25/K Parametric

Parameter NameAttribute value
Is it lead-free?Contains lead
Is it Rohs certified?incompatible
Parts packaging codeQFJ
package instructionQCCN, LCC32,.45X.55
Contacts32
Reach Compliance Code_compli
ECCN codeEAR99
Maximum access time250 ns
Other featuresAUTOMATIC WRITE
command user interfaceNO
Data pollingYES
Durability10000 Write/Erase Cycles
JESD-30 codeR-CQCC-N32
JESD-609 codee0
length13.97 mm
memory density4096 bi
Memory IC TypeEEPROM
memory width8
Number of functions1
Number of terminals32
word count512 words
character code512
Operating modeASYNCHRONOUS
Maximum operating temperature70 °C
Minimum operating temperature
organize512X8
Output characteristics3-STATE
Package body materialCERAMIC, METAL-SEALED COFIRED
encapsulated codeQCCN
Encapsulate equivalent codeLCC32,.45X.55
Package shapeRECTANGULAR
Package formCHIP CARRIER
Parallel/SerialPARALLEL
Peak Reflow Temperature (Celsius)NOT SPECIFIED
power supply5 V
Programming voltage5 V
Certification statusNot Qualified
Maximum seat height3.048 mm
Maximum standby current0.0001 A
Maximum slew rate0.03 mA
Maximum supply voltage (Vsup)5.5 V
Minimum supply voltage (Vsup)4.5 V
Nominal supply voltage (Vsup)5 V
surface mountYES
technologyCMOS
Temperature levelCOMMERCIAL
Terminal surfaceTin/Lead (Sn/Pb)
Terminal formNO LEAD
Terminal pitch1.27 mm
Terminal locationQUAD
Maximum time at peak reflow temperatureNOT SPECIFIED
switch bitNO
width11.43 mm
Maximum write cycle time (tWC)0.2 ms
Base Number Matches1
28C04A
4K (512 x 8) CMOS EEPROM
FEATURES
• Fast Read Access Time—150 ns
• CMOS Technology for Low Power Dissipation
- 30 mA Active
- 100
µ
A Standby
• Fast Byte Write Time—200
µ
s or 1 ms
• Data Retention >200 years
• Endurance - Minimum 10
4
Erase/Write Cycles
- Automatic Write Operation
- Internal Control Timer
- Auto-Clear Before Write Operation
- On-Chip Address and Data Latches
• Data Polling
• Chip Clear Operation
• Enhanced Data Protection
- V
CC
Detector
- Pulse Filter
- Write Inhibit
• 5-Volt-Only Operation
• Organized 512x8 JEDEC standard pinout
- 24-pin Dual-In-Line Package
- 32-pin PLCC Package
• Available for Extended Temperature Ranges:
- Commercial: 0˚C to +70˚C
- Industrial: -40˚C to +85˚C
PACKAGE TYPES
DIP
A7
A6
A5
A4
A3
A2
A1
A0
I/O0
I/O1
I/O2
V
SS
•1
2
3
4
5
6
7
8
9
10
11
12
24
23
22
21
20
19
18
17
16
15
14
13
Vcc
A8
NC
WE
OE
NC
CE
I/O7
I/O6
I/O5
I/O4
I/O3
32
Vcc
31
WE
18
19
28C04A
2
NC
1
NU
4
A7
3
NC
PLCC
A6
A5
A4
A3
A2
A1
A0
NC
I/O0
5
6
7
8
9
10
11
12
13
30
NC
29
A8
28
NC
27
NC
26
NC
25
OE
24
NC
23
CE
22
I/O7
21
I/O6
20
28C04A
14
15
16
Pin 1 indicator on PLCC on top of package
BLOCK DIAGRAM
I/O0
I/O7
DESCRIPTION
The Microchip Technology Inc. 28C04A is a CMOS 4K
non-volatile electrically Erasable and Programmable
Read Only Memory (EEPROM). The 28C04A is
accessed like a static RAM for the read or write cycles
without the need of external components. During a
“byte write”, the address and data are latched internally,
freeing the microprocessor address and data bus for
other operations. Following the initiation of write cycle,
the device will go to a busy state and automatically
clear and write the latched data using an internal con-
trol timer. To determine when a write cycle is complete,
the 28C04A uses Data polling. Data polling allows the
user to read the location last written to when the write
operation is complete. CMOS design and processing
enables this part to be used in systems where reduced
power consumption and reliability are required. A com-
plete family of packages is offered to provide the utmost
flexibility in applications.
V
SS
V
CC
CE
OE
WE
Data Protection
Circuitry
Chip Enable/
Output Enable
Control Logic
Auto Erase/Write
Timing
I/O1
I/O2
Vss
NU
I/O3
I/O4
I/O5
17
Data
Poll
Input/Output
Buffers
Program Voltage
Generation
A0
L
a
t
c
h
e
s
A8
Y
Decoder
Y Gating
X
Decoder
4K bit
Cell Matrix
©
1996 Microchip Technology Inc.
DS11126F-page 1
This document was created with FrameMaker 4 0 4
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