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MT55L256V18P1T-10A

Description
ZBT SRAM, 256KX18, 5ns, CMOS, PQFP100, PLASTIC, MS-026BHA, TQFP-100
Categorystorage    storage   
File Size456KB,26 Pages
ManufacturerCypress Semiconductor
Download Datasheet Parametric View All

MT55L256V18P1T-10A Overview

ZBT SRAM, 256KX18, 5ns, CMOS, PQFP100, PLASTIC, MS-026BHA, TQFP-100

MT55L256V18P1T-10A Parametric

Parameter NameAttribute value
Is it Rohs certified?incompatible
MakerCypress Semiconductor
Parts packaging codeQFP
package instructionLQFP,
Contacts100
Reach Compliance Codeunknown
ECCN code3A991.B.2.A
Maximum access time5 ns
JESD-30 codeR-PQFP-G100
JESD-609 codee0
length20 mm
memory density4718592 bit
Memory IC TypeZBT SRAM
memory width18
Humidity sensitivity level3
Number of functions1
Number of terminals100
word count262144 words
character code256000
Operating modeSYNCHRONOUS
Maximum operating temperature70 °C
Minimum operating temperature
organize256KX18
Package body materialPLASTIC/EPOXY
encapsulated codeLQFP
Package shapeRECTANGULAR
Package formFLATPACK, LOW PROFILE
Parallel/SerialPARALLEL
Peak Reflow Temperature (Celsius)NOT SPECIFIED
Certification statusNot Qualified
Maximum seat height1.6 mm
Maximum supply voltage (Vsup)3.465 V
Minimum supply voltage (Vsup)3.135 V
Nominal supply voltage (Vsup)3.3 V
surface mountYES
technologyCMOS
Temperature levelCOMMERCIAL
Terminal surfaceTIN LEAD
Terminal formGULL WING
Terminal pitch0.65 mm
Terminal locationQUAD
Maximum time at peak reflow temperatureNOT SPECIFIED
width14 mm
PRELIMINARY
4Mb: 256K x 18, 128K x 32/36
PIPELINED ZBT SRAM
4Mb ZBT
SRAM
WITH S
MART
ZBT OPTION
FEATURES
• S
MART
ZBT™ option to minimize potential bus
contention
• High frequency and 100 percent bus utilization
• Fast cycle times: 6ns, 7.5ns and 10ns
• Single +3.3V
±5%
power supply (V
DD
)
• Separate +3.3V or +2.5V isolated output buffer
supply (V
DD
Q)
• Advanced control logic for minimum control
signal interface
• Individual BYTE WRITE controls may be tied LOW
• Single R/W# (read/write) control pin
• CKE# pin to enable clock and suspend operations
• Three chip enables for simple depth expansion
• Clock-controlled and registered addresses, data
I/Os and control signals
• Internally self-timed, fully coherent WRITE
• Internally self-timed, registered outputs to
eliminate the need to control OE#
• SNOOZE MODE for reduced-power standby
• Common data inputs and data outputs
• Linear or interleaved burst modes
• Burst feature (optional)
• Pin/function compatibility with 2Mb, 8Mb and
16Mb ZBT SRAM family
• Automatic power-down
MT55L256L18P1, MT55L256V18P1,
MT55L128L32P1, MT55L128V32P1,
MT55L128L36P1, MT55L128V36P1
3.3V V
DD
, 3.3V or 2.5V I/O
100-Pin TQFP**
119-Pin BGA
OPTIONS
• Timing (Access/Cycle/MHz)
4ns/6ns/166 MHz
4.2ns/7.5ns/133 MHz
5ns/10ns/100 MHz
• Configurations
3.3V I/O
256K x 18
128K x 32
128K x 36
2.5V I/O
256K x 18
128K x 32
128K x 36
• Package
100-pin TQFP
119-pin, 14mm x 22mm BGA
*S
MART
ZBT option available.
Part Number Example:
MARKING
-6
-7.5*
-10*
**JEDEC-standard MS-026 BHA (LQFP).
MT55L256L18P1
MT55L128L32P1
MT55L128L36P1
MT55L256V18P1
MT55L128V32P1
MT55L128V36P1
T
B
GENERAL DESCRIPTION
The Micron
®
Zero Bus Turnaround
(ZBT
) SRAM
family employs high-speed, low-power CMOS designs
using an advanced CMOS process.
The S
MART
ZBT feature enhances the ability of the
SRAM to run in systems with minimal transition time
on the data bus, whether using multiple SRAMs or
complementing ASIC designs.
Micron’s S
MART
ZBT feature allows the
t
KHQX1 (clock
HIGH to output valid) to adapt to the system clock, thus
reducing contention issues. The S
MART
ZBT will drive
the bus turn-on later than the traditional ZBT.
MT55L256L18P1T-10A
4Mb: 256K x 18, 128K x 32/36 Pipelined ZBT SRAM
MT55L256L18P1.p65 – Rev. 3/00
1
Micron Technology, Inc., reserves the right to change products or specifications without notice.
©2000, Micron Technology, Inc.
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