Philips Semiconductors
Product specification
Silicon Diffused Power Transistor
BUT11F
GENERAL DESCRIPTION
High-voltage, high-speed glass-passivated npn power transistor in a SOT186 envelope with electrically insulated
mounting base,intended for use in converters, inverters, switching regulators, motor control systems, etc.
QUICK REFERENCE DATA
SYMBOL
V
CESM
V
CEO
I
C
I
CM
P
tot
V
CEsat
I
Csat
t
f
PARAMETER
Collector-emitter voltage peak value
Collector-emitter voltage (open base)
Collector current (DC)
Collector current peak value
Total power dissipation
Collector-emitter saturation voltage
Collector saturation current
Fall time
CONDITIONS
V
BE
= 0 V
TYP.
-
-
-
-
-
-
-
-
MAX.
850
400
5
10
20
1.5
3
800
UNIT
V
V
A
A
W
V
A
ns
T
hs
≤
25 ˚C
[INCLUDE]
LIMITING VALUES
Limiting values in accordance with the Absolute Maximum Rating System (IEC 134)
SYMBOL
V
CESM
V
CEO
I
C
I
CM
I
B
I
BM
P
tot
T
stg
T
j
PARAMETER
Collector-emitter voltage peak value
Collector-emitter voltage (open base)
Collector current (DC)
Collector current peak value
Base current (DC)
Base current peak value
Total power dissipation
Storage temperature
Junction temperature
CONDITIONS
V
BE
= 0 V
MIN.
-
-
-
-
-
-
-
-65
-
MAX.
850
450
5
10
2
4
20
150
150
UNIT
V
V
A
A
A
A
W
˚C
˚C
T
hs
≤
25 ˚C
THERMAL RESISTANCES
SYMBOL
R
th j-hs
R
th j-a
PARAMETER
Junction to heatsink
Junction to ambient
CONDITIONS
with heatsink compound
in free air
TYP.
-
55
MAX.
3.95
-
UNIT
K/W
K/W
ISOLATION LIMITING VALUE & CHARACTERISTIC
T
hs
= 25 ˚C unless otherwise specified
SYMBOL
V
isol
PARAMETER
Repetitive peak voltage from all
three terminals to external
heatsink
CONDITIONS
R.H.
≤
65% ; clean and dustfree
MIN.
-
TYP.
MAX.
1500
UNIT
V
C
isol
Capacitance from T2 to external f = 1 MHz
heatsink
-
12
-
pF
August 1997
1
Rev 1.000
Philips Semiconductors
Product specification
Silicon Diffused Power Transistor
BUT11F
STATIC CHARACTERISTICS
T
hs
= 25 ˚C unless otherwise specified
SYMBOL
I
CES
I
CES
I
EBO
V
CEOsust
V
CEsat
V
BEsat
h
FE
h
FE
PARAMETER
Collector cut-off current
1
CONDITIONS
MIN.
-
-
-
450
-
-
10
10
TYP.
-
-
-
-
-
-
18
20
MAX.
1.0
2.0
10
-
1.5
1.3
35
35
UNIT
mA
mA
mA
V
V
V
V
BE
= 0 V; V
CE
= V
CESMmax
V
BE
= 0 V; V
CE
= V
CESMmax
;
T
j
= 125 ˚C
Emitter cut-off current
V
EB
= 9 V; I
C
= 0 A
Collector-emitter sustaining voltage I
B
= 0 A; I
C
= 100 mA;
L = 25 mH
Collector-emitter saturation voltages I
C
= 3.0 A; I
B
= 0.6 A
Base-emitter saturation voltage
I
C
= 3.0 A; I
B
= 0.6 A
DC current gain
I
C
= 5 mA; V
CE
= 5 V
I
C
= 500 mA; V
CE
= 5 V
DYNAMIC CHARACTERISTICS
T
hs
= 25 ˚C unless otherwise specified
SYMBOL
t
on
t
s
t
f
PARAMETER
Switching times (resistive load)
Turn-on time
Turn-off storage time
Turn-off fall time
Switching times (inductive load)
t
s
t
f
Turn-off storage time
Turn-off fall time
Switching times (inductive load)
t
s
t
f
Turn-off storage time
Turn-off fall time
CONDITIONS
I
Con
= 2.5 A; I
Bon
= -I
Boff
= 0.5 A
TYP.
-
-
-
MAX.
1
4
0.8
UNIT
µs
µs
µs
µs
ns
µs
ns
I
Con
= 2.5 A; I
Bon
= 0.5 A; L
B
= 1
µH;
-V
BB
= 5 V
I
Con
= 2.5 A; I
Bon
= 0.5 A; L
B
= 1
µH;
-V
BB
= 5 V; T
j
= 100 ˚C
1.1
80
1.4
150
1.2
140
1.5
300
IC / mA
+ 50v
100-200R
250
Horizontal
Oscilloscope
Vertical
300R
30-60 Hz
6V
1R
200
100
0
VCE / V
min
VCEOsust
Fig.1. Test circuit for V
CEOsust
.
Fig.2. Oscilloscope display for V
CEOsust
.
1
Measured with half sine-wave voltage (curve tracer).
August 1997
2
Rev 1.000
Philips Semiconductors
Product specification
Silicon Diffused Power Transistor
BUT11F
VCC
ICon
90 %
IC
RL
VIM
0
tp
IB
RB
T.U.T.
ts
toff
IBon
10 %
tf
t
T
-IBoff
t
Fig.3. Test circuit resistive load. V
IM
= -6 to +8 V
V
CC
= 250 V; t
p
= 20
µ
s;
δ
= t
p
/ T = 0.01.
R
B
and R
L
calculated from I
Con
and I
Bon
requirements.
Fig.6. Switching times waveforms with inductive load.
90 %
ICon
90 %
120
110
100
90
%
Normalised Derating
with heatsink compound
IC
10 %
ts
ton
toff
IBon
10 %
tr
30ns
-IBoff
tf
80
70
60
50
40
30
20
10
0
0
20
40
60
80
Ths / C
100
120
140
P tot
IB
Fig.4. Switching times waveforms with resistive load.
Fig.7. Normalised power derating and second
breakdown curves.
VCC
6
5
4
IC / A
BUT11AX
LC
3
IBon
LB
T.U.T.
2
1
0
0
400
VCE / V
800
1200
-VBB
Fig.5. Test circuit inductive load.
V
CC
= 300 V; -V
BE
= 5 V; L
C
= 200 uH; L
B
= 1 uH
Fig.8. Reverse bias safe operating area. T
j
≤
T
j max
August 1997
3
Rev 1.000
Philips Semiconductors
Product specification
Silicon Diffused Power Transistor
BUT11F
100
h FE
BUT11AX
100
IC / A
5V
10
1V
ICM max
10
IC max
= 0.01
tp =
10 us
II
(1)
100 us
1
0.01
1
0.1
1
IC / A
10
100
1 ms
10 ms
Fig.9. Typical DC current gain.
h
FE
= f(I
C
); parameter V
CE
0.1
I
(2)
500 ms
DC
III
0.01
1
10
100
VCE / V
1000
Fig.10. Forward bias safe operating area. T
hs
≤
25 ˚C
(1)
(2)
I
II
III
NB:
P
tot
max and P
tot
peak max lines.
Second breakdown limits.
Region of permissible DC operation.
Extension for repetitive pulse operation.
Extension during turn-on in single
transistor converters provided that
R
BE
≤
100
Ω
and t
p
≤
0.6
µ
s.
Mounted with heatsink compound and
30
±
5 newton force on the centre of the
envelope.
August 1997
4
Rev 1.000
Philips Semiconductors
Product specification
Silicon Diffused Power Transistor
BUT11F
Fig.11. Typical base-emitter and collector-emitter saturation voltages.
V
BEsat
= f(I
C
); V
CEsat
= f(I
C
); I
C
/I
B
= 5
Fig.12. Collector-emitter saturation voltage. Solid lines = typ values,
dotted lines = max values. V
CEsat
= f(I
B
); parameter I
C
August 1997
5
Rev 1.000
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