DS21Q48 datasheet, PDF - EEWORLD Datasheet

Datasheet> All Categories > Wireless rf/communication> Telecom circuit> DS21Q48

DS21Q48: DescriptionDATACOM, PCM TRANSCEIVER, PBGA144, 17 X 17 MM, CSBGA-144; CategoryWireless rf/communication Telecom circuit; File Size2MB，76 Pages; ManufacturerRochester Electronics; Websitehttps://www.rocelec.com/; Related ProductsFound3parts with similar functions to DS21Q48

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DS21Q48 Overview

DATACOM, PCM TRANSCEIVER, PBGA144, 17 X 17 MM, CSBGA-144

DS21Q48 Parametric

Parameter Name	Attribute value
Is it lead-free?	Contains lead
Is it Rohs certified?	incompatible
Maker	Rochester Electronics
Parts packaging code	BGA
package instruction	17 X 17 MM, CSBGA-144
Contacts	144
Reach Compliance Code	unknown
JESD-30 code	S-PBGA-B144
JESD-609 code	e0
length	17 mm
Humidity sensitivity level	NOT SPECIFIED
Number of functions	1
Number of terminals	144
Maximum operating temperature	70 °C
Minimum operating temperature
Package body material	PLASTIC/EPOXY
encapsulated code	BGA
Package shape	SQUARE
Package form	GRID ARRAY
Peak Reflow Temperature (Celsius)	240
Certification status	COMMERCIAL
Nominal supply voltage	5 V
surface mount	YES
technology	CMOS
Telecom integrated circuit types	PCM TRANSCEIVER
Temperature level	COMMERCIAL
Terminal surface	TIN LEAD
Terminal form	BALL
Terminal pitch	1.27 mm
Terminal location	BOTTOM
Maximum time at peak reflow temperature	NOT SPECIFIED
width	17 mm

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DS2148/DS21Q48

TABLE OF CONTENTS

DETAILED DESCRIPTION .................................................................................................. 5

1.1

1.2

UNCTION

ESCRIPTION

..................................................................................................................5

OCUMENT

EVISION

ISTORY

.......................................................................................................6

PIN DESCRIPTION............................................................................................................ 10

HARDWARE MODE .......................................................................................................... 23

3.1

3.2

3.3

EGISTER

.............................................................................................................................23

ARALLEL

ORT

PERATION

.........................................................................................................24

ERIAL

ORT

PERATION

..............................................................................................................24

EVICE

OWER

-U

P AND

ESET

.....................................................................................................31

CONTROL REGISTERS .................................................................................................... 28

4.1

STATUS REGISTERS ....................................................................................................... 34

DIAGNOSTICS .................................................................................................................. 39

6.1 I

-B

AND

OOP

ODE

ENERATION AND

ETECTION

......................................................................39

6.2 L

OOPBACKS

..................................................................................................................................43

6.2.1 Remote Loopback (RLB) ......................................................................................................43

6.2.2

6.2.3

Local Loopback (LLB) ...........................................................................................................43

Analog Loopback (ALB) ........................................................................................................44

6.2.4 Dual Loopback (DLB)............................................................................................................44

6.3 PRBS G

ENERATION AND

ETECTION

............................................................................................44

6.4 E

RROR

OUNTER

..........................................................................................................................44

6.4.1 Error Counter Update............................................................................................................45

6.5 E

RROR

NSERTION

........................................................................................................................45

ANALOG INTERFACE ...................................................................................................... 46

7.1

7.2

7.3

7.4

ECEIVER

.....................................................................................................................................46

RANSMITTER

...............................................................................................................................47

ITTER

TTENUATOR

.....................................................................................................................47

G.703 S

YNCHRONIZATION

IGNAL

.................................................................................................48

DS21Q48 QUAD LIU ......................................................................................................... 55

DC CHARACTERISTICS ................................................................................................... 59

9.1

THERMAL CHARACTERISTICS ................................................................................................60

10 AC CHARACTERISTICS ................................................................................................... 61

11 PACKAGE INFORMATION ............................................................................................... 70

11.1 44-P

TQFP (56-G4012-001) .....................................................................................................70

11.2 49-B

ALL

CSGBA (7

MM X

) (56-G6006-001) ...........................................................................71

11.3 144-B

ALL

CSBGA (17

MM X

) (56-G6011-001) .....................................................................72

2 of 73

DS2148/DS21Q48

LIST OF FIGURES

Figure 1-1. DS2148 Block Diagram ............................................................................................................7

Figure 1-2. Receive Logic...........................................................................................................................8

Figure 1-3. Transmit Logic..........................................................................................................................9

Figure 2-1. Parallel Port Mode Pinout (BIS1 = 0, BIS0 = 1 or 0) (TQFP Package) ..................................21

Figure 2-2. Serial Port Mode Pinout (BIS1 = 1, BIS0 = 0) (TQFP Package) ............................................21

Figure 2-3. Hardware Mode Pinout (BIS1 = 1, BIS0 = 1) (TQFP Package) .............................................22

Figure 3-1. Serial Port Operation for Read Access (R = 1) Mode 1 .........................................................25

Figure 3-2. Serial Port Operation for Read Access Mode 2 .....................................................................25

Figure 3-3. Serial Port Operation for Read Access Mode 3 .....................................................................26

Figure 3-4. Serial Port Operation for Read Access Mode 4 .....................................................................26

Figure 3-5. Serial Port Operation for Write Access (R = 0) Modes 1 and 2..............................................27

Figure 3-6. Serial Port Operation for Write Access (R = 0) Modes 3 and 4..............................................27

Figure 7-1. Basic Interface .......................................................................................................................49

Figure 7-2. Protected Interface Using Internal Receive Termination........................................................50

Figure 7-3. Protected Interface Using External Receive Termination.......................................................51

Figure 7-4. E1 Transmit Pulse Template ..................................................................................................52

Figure 7-5. T1 Transmit Pulse Template ..................................................................................................53

Figure 7-6. Jitter Tolerance ......................................................................................................................54

Figure 7-7. Jitter Attenuation ....................................................................................................................54

Figure 8-1. 144-Pin CSBGA (17mm x 17mm) Pinout ...............................................................................58

Figure 10-1. Intel Bus Read Timing (PBTS = 0, BIS1 = 0, BIS0 = 0) .......................................................62

Figure 10-2. Intel Bus Write Timing (PBTS = 0, BIS1 = 0, BIS0 = 0) .......................................................62

Figure 10-3. Motorola Bus Timing (PBTS = 1, BIS1 = 0, BIS0 = 0)..........................................................63

Figure 10-4. Intel Bus Read Timing (PBTS = 0, BIS1 = 0, BIS0 = 1) .......................................................65

Figure 10-5. Intel Bus Write Timing (PBTS = 0, BIS1 = 0, BIS0 = 1) .......................................................65

Figure 10-6. Motorola Bus Read Timing (PBTS = 1, BIS1 = 0, BIS0 = 1) ................................................66

Figure 10-7. Motorola Bus Write Timing (PBTS = 1, BIS1 = 0, BIS0 = 1) ................................................66

Figure 10-8. Serial Bus Timing (BIS1 = 1, BIS0 = 0) ................................................................................67

Figure 10-9. Receive Side Timing ............................................................................................................68

Figure 10-10. Transmit Side Timing .........................................................................................................69

3 of 73

DS2148/DS21Q48

LIST OF TABLES

Table 2-1. Bus Interface Selection ...........................................................................................................10

Table 2-2. Pin Assignment in Parallel Port Mode .....................................................................................10

Table 2-3. Pin Descriptions in Parallel Port Mode (Sorted by Pin Name, DS2148T) ...............................12

Table 2-4. Pin Assignment in Serial Port Mode ........................................................................................14

Table 2-5. Pin Descriptions in Serial Port Mode (Sorted by Pin Name, DS2148T) ..................................15

Table 2-6. Pin Assignment in Hardware Mode .........................................................................................17

Table 2-7. Pin Description in Hardware Mode (Sorted by Pin Name, DS2148T) .....................................18

Table 2-8. Loopback Control in Hardware Mode ......................................................................................20

Table 2-9. Transmit Data Control in Hardware Mode ...............................................................................20

Table 2-10. Receive Sensitivity Settings ..................................................................................................20

Table 2-11. Monitor Gain Settings ............................................................................................................20

Table 2-12. Internal Rx Termination Select ..............................................................................................20

Table 2-13. MCLK Selection.....................................................................................................................20

Table 3-1. Register Map ...........................................................................................................................23

Table 4-1. MCLK Selection.......................................................................................................................29

Table 4-2. Receive Sensitivity Settings ....................................................................................................31

Table 4-3. Backplane Clock Select...........................................................................................................32

Table 4-4. Monitor Gain Settings ..............................................................................................................32

Table 4-5. Internal Rx Termination Select ................................................................................................33

Table 5-1. Received Alarm Criteria ..........................................................................................................35

Table 5-2. Receive Level Indication .........................................................................................................38

Table 6-1. Transmit Code Length .............................................................................................................40

Table 6-2. Receive Code Length..............................................................................................................40

Table 6-3. Definition of Received Errors...................................................................................................44

Table 6-4. Function of ECRS Bits and RNEG Pin ....................................................................................45

Table 7-1. Line Build-Out Select for E1 in Register CCR4 (ETS = 0).......................................................48

Table 7-2. Line Build-Out Select for T1 in Register CCR4 (ETS = 1).......................................................48

Table 7-3. Transformer Specifications for 5V Operation ..........................................................................48

Table 8-1. DS21Q48 Pin Assignment.......................................................................................................55

Table 9-1. Recommended DC Operating Conditions ...............................................................................59

Table 9-2. Capacitance ............................................................................................................................59

Table 9-3. DC Characteristics ..................................................................................................................59

Table 9-4. Thermal Characteristics—DS21Q48 CSBGA Package...........................................................60

Table 9-5. Theta-JA (θ

) vs. Airflow ........................................................................................................60

Table 10-1. AC Characteristics—Multiplexed Parallel Port (BIS1 = 0, BIS0 = 0) ....................................61

Table 10-2. AC Characteristics—Nonmultiplexed Parallel Port (BIS1 = 0, BIS0 = 1)..............................64

Table 10-3. AC Characteristics—Serial Port (BIS1 = 1, BIS0 = 0) ...........................................................67

Table 10-4. AC Characteristics—Receive Side ........................................................................................68

Table 10-5. AC Characteristics—Transmit Side .......................................................................................69

4 of 73

DS21Q48 Related Products

	DS21Q48	DS2148TN	DS2148G	DS2148TA2
Description	DATACOM, PCM TRANSCEIVER, PBGA144, 17 X 17 MM, CSBGA-144	DATACOM, PCM TRANSCEIVER, PQFP44, 10 X 10 MM, 1 MM HEIGHT, TQFP-44	DATACOM, PCM TRANSCEIVER, PBGA49, 7 X 7 MM, CSBGA-49	DATACOM, PCM TRANSCEIVER, PQFP44, 10 X 10 MM, 1 MM HEIGHT, TQFP-44
Is it lead-free?	Contains lead	Contains lead	Contains lead	Contains lead
Is it Rohs certified?	incompatible	incompatible	incompatible	incompatible
Maker	Rochester Electronics	Rochester Electronics	Rochester Electronics	Rochester Electronics
Parts packaging code	BGA	QFP	BGA	QFP
package instruction	17 X 17 MM, CSBGA-144	TQFP,	LFBGA,	TQFP,
Contacts	144	44	49	44
Reach Compliance Code	unknown	unknown	unknown	unknown
JESD-30 code	S-PBGA-B144	S-PQFP-G44	S-PBGA-B49	S-PQFP-G44
length	17 mm	10 mm	7 mm	10 mm
Humidity sensitivity level	NOT SPECIFIED	3	3	4
Number of functions	1	1	1	1
Number of terminals	144	44	49	44
Maximum operating temperature	70 °C	85 °C	70 °C	70 °C
Package body material	PLASTIC/EPOXY	PLASTIC/EPOXY	PLASTIC/EPOXY	PLASTIC/EPOXY
encapsulated code	BGA	TQFP	LFBGA	TQFP
Package shape	SQUARE	SQUARE	SQUARE	SQUARE
Package form	GRID ARRAY	FLATPACK, THIN PROFILE	GRID ARRAY, LOW PROFILE, FINE PITCH	FLATPACK, THIN PROFILE
Peak Reflow Temperature (Celsius)	240	240	240	245
Certification status	COMMERCIAL	COMMERCIAL	COMMERCIAL	COMMERCIAL
Nominal supply voltage	5 V	5 V	5 V	5 V
surface mount	YES	YES	YES	YES
technology	CMOS	CMOS	CMOS	CMOS
Telecom integrated circuit types	PCM TRANSCEIVER	PCM TRANSCEIVER	PCM TRANSCEIVER	PCM TRANSCEIVER
Temperature level	COMMERCIAL	INDUSTRIAL	COMMERCIAL	COMMERCIAL
Terminal surface	TIN LEAD	TIN LEAD	NOT SPECIFIED	TIN LEAD
Terminal form	BALL	GULL WING	BALL	GULL WING
Terminal pitch	1.27 mm	0.8 mm	0.8 mm	0.8 mm
Terminal location	BOTTOM	QUAD	BOTTOM	QUAD
Maximum time at peak reflow temperature	NOT SPECIFIED	20	20	NOT SPECIFIED
width	17 mm	10 mm	7 mm	10 mm
JESD-609 code	e0	e0	-	e0
Maximum seat height	-	1.2 mm	1.5 mm	1.2 mm

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DS21Q48 Similar Products

Part Number	Manufacturer	Description
DS21Q48	DALLAS	DATACOM, PCM TRANSCEIVER, PBGA144
DS21Q48N	Maxim(美信半导体)	Telecom Interface ICs 5V Quad E1/T1/J1 Line Interface
DS21Q48N	DALLAS	DATACOM, PCM TRANSCEIVER, PBGA144

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