56F801
Data Sheet
Preliminary Technical Data
56F800
16-bit Digital Signal Controllers
DSP56F801
Rev. 17
09/2007
freescale.com
Document Revision History
Version History
Rev. 17
Description of Change
Added revision history.
Added this text to footnote 2 in
Table 3-8:
“However, the high pulse width does not have to
be any particular percent of the low pulse width.”
56F801 General Description
• Up to 30 MIPS operation at 60MHz core frequency
• Up to 40 MIPS operation at 80MHz core frequency
• DSP and MCU functionality in a unified,
C-efficient architecture
• MCU-friendly instruction set supports both DSP and
controller functions: MAC, bit manipulation unit, 14
addressing modes
• Hardware DO and REP loops
• 6-channel PWM Module
• Two 4-channel, 12-bit ADCs
• Serial Communications Interface (SCI)
• Serial Peripheral Interface (SPI)
• 8K
×
16-bit words (16KB) Program Flash
• 1K
×
16-bit words (2KB) Program RAM
• 2K
×
16-bit words (4KB) Data Flash
• 1K
×
16-bit words (2KB) Data RAM
• 2K
×
16-bit words (4KB) Boot Flash
• General Purpose Quad Timer
• JTAG/OnCE
TM
port for debugging
• On-chip relaxation oscillator
• 11 shared GPIO
• 48-pin LQFP Package
6
PWM Outputs
PWMA
RESET
IRQA
6
JTAG/
OnCE
Port
VCAPC V
DD
2
4
V
SS
5*
Digital Reg
Analog Reg
V
DDA
V
SSA
Fault Input
4
4
A/D1
A/D2
VREF
ADC
Interrupt
Controller
Low Voltage
Supervisor
Program Controller
and
Hardware Looping Unit
Address
Generation
Unit
Data ALU
16 x 16 + 36
→
36-Bit MAC
Three 16-bit Input Registers
Two 36-bit Accumulators
Bit
Manipulation
Unit
Quad Timer C
Quad Timer D
or GPIO
Program Memory
8188 x 16 Flash
1024 x 16 SRAM
Boot Flash
2048 x 16 Flash
Data Memory
2048 x 16 Flash
1024 x 16 SRAM
•
PAB
•
•
PDB
•
•
•
•
IPBB
CONTROLS
16
PLL
3
XDB2
CGDB
XAB1
XAB2
16-Bit
56800
Core
Clock Gen
or Optional
Internal
Relaxation Osc.
GPIOB3/XTAL
GPIOB2/EXTAL
•
2
SCI0
or
GPIO
INTERRUPT
CONTROLS
16
COP/
Watchdog
COP RESET
MODULE CONTROLS
ADDRESS BUS [8:0]
DATA BUS [15:0]
4
SPI
or
GPIO
Applica-
tion-Specific
Memory &
Peripherals
IPBus Bridge
(IPBB)
*
includes TCS pin which is reserved for factory use and is tied to VSS
56F801 Block Diagram
56F801 Technical Data, Rev. 17
Freescale Semiconductor
3
Part 1 Overview
1.1 56F801 Features
1.1.1
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Digital Signal Processing Core
Efficient 16-bit 56800 family controller engine with dual Harvard architecture
As many as 40 Million Instructions Per Second (MIPS) at 80MHz core frequency
Single-cycle 16
×
16-bit parallel Multiplier-Accumulator (MAC)
Two 36-bit accumulators including extension bits
16-bit bidirectional barrel shifter
Parallel instruction set with unique processor addressing modes
Hardware DO and REP loops
Three internal address buses and one external address bus
Four internal data buses and one external data bus
Instruction set supports both DSP and controller functions
Controller style addressing modes and instructions for compact code
Efficient C compiler and local variable support
Software subroutine and interrupt stack with depth limited only by memory
JTAG/OnCE debug programming interface
1.1.2
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•
Memory
Harvard architecture permits as many as three simultaneous accesses to Program and Data memory
On-chip memory including a low-cost, high-volume Flash solution
— 8K
×
16 bit words of Program Flash
— 1K
×
16-bit words of Program RAM
— 2K
×
16-bit words of Data Flash
— 1K
×
16-bit words of Data RAM
— 2K
×
16-bit words of Boot Flash
•
Programmable Boot Flash supports customized boot code and field upgrades of stored code through a
variety of interfaces (JTAG, SPI)
1.1.3
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Peripheral Circuits for 56F801
Pulse Width Modulator (PWM) with six PWM outputs, two Fault inputs, fault-tolerant design with deadtime
insertion; supports both center- and edge-aligned modes
Two 12-bit, Analog-to-Digital Converters (ADCs), which support two simultaneous conversions with two
4-multiplexed inputs; ADC and PWM modules can be synchronized
General Purpose Quad Timer: Timer D with three pins (or three additional GPIO lines)
Serial Communication Interface (SCI) with two pins (or two additional GPIO lines)
Serial Peripheral Interface (SPI) with configurable four-pin port (or four additional GPIO lines)
56F801 Technical Data, Rev. 17
4
Freescale Semiconductor
56F801 Description
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Eleven multiplexed General Purpose I/O (GPIO) pins
Computer-Operating Properly (COP) watchdog timer
One dedicated external interrupt pin
External reset pin for hardware reset
JTAG/On-Chip Emulation (OnCE™) for unobtrusive, processor speed-independent debugging
Software-programmable, Phase Locked Loop-based frequency synthesizer for the controller core clock
Oscillator flexibility between either an external crystal oscillator or an on-chip relaxation oscillator for
lower system cost and two additional GPIO lines
1.1.4
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Energy Information
Fabricated in high-density CMOS with 5V-tolerant, TTL-compatible digital inputs
Uses a single 3.3V power supply
On-chip regulators for digital and analog circuitry to lower cost and reduce noise
Wait and Stop modes available
1.2 56F801 Description
The 56F801 is a member of the 56800 core-based family of processors. It combines, on a single chip, the
processing power of a DSP and the functionality of a microcontroller with a flexible set of peripherals to
create an extremely cost-effective solution. Because of its low cost, configuration flexibility, and
compact program code, the 56F801 is well-suited for many applications. The 56F801 includes many
peripherals that are especially useful for applications such as motion control, smart appliances, steppers,
encoders, tachometers, limit switches, power supply and control, automotive control, engine
management, noise suppression, remote utility metering, and industrial control for power, lighting, and
automation.
The 56800 core is based on a Harvard-style architecture consisting of three execution units operating in
parallel, allowing as many as six operations per instruction cycle. The microprocessor-style programming
model and optimized instruction set allow straightforward generation of efficient, compact code for both
DSP and MCU applications. The instruction set is also highly efficient for C compilers to enable rapid
development of optimized control applications.
The 56F801 supports program execution from either internal or external memories. Two data operands can
be accessed from the on-chip Data RAM per instruction cycle. The 56F801 also provides one external
dedicated interrupt lines and up to 11 General Purpose Input/Output (GPIO) lines, depending on peripheral
configuration.
The 56F801 controller includes 8K words (16-bit) of Program Flash and 2K words of Data Flash (each
programmable through the JTAG port) with 1K words of both Program and Data RAM. A total of 2K
words of Boot Flash is incorporated for easy customer-inclusion of field-programmable software routines
that can be used to program the main Program and Data Flash memory areas. Both Program and Data Flash
memories can be independently bulk erased or erased in page sizes of 256 words. The Boot Flash memory
can also be either bulk or page erased.
56F801 Technical Data, Rev. 17
Freescale Semiconductor
5
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