CY28372
SiS 746 AMD Athlon™/AMD Duron™ Clock Synthesizer
Features
•
Supports AMD Athlon™/Duron™ CPU
• 3.3V and 2.5V power supply
• Eight copies of PCI clocks
• One 48-MHz USB clock
• Two copies of ZCLK clocks
• One 48 MHz/24 MHz programmable SIO clock
CPU
x2
ZCLK
x2
REF
x3
PCI
x8
AGP
x2
IOAPIC
x2
48M
x1
24_48M
x1
• One differential CPU clock (opendrain)
• One singled-ended CPU clock (opendrain)
• SMBus support with readback capabilities
• Spread Spectrum electromagnetic interference (EMI)
reduction
•
48-pin SSOP package
Block Diagram
XIN
XOUT
Pin Configuration
VDD_REF
REF0:2
XTAL
OSC
PLL Ref Freq
Divider
Network
VDD_CPU
CPUT1
CPUT0, CPUC0
VDD_Z
ZCLK0:1
PLL 1
**FS0:3
CPU_STP#
VDD_APIC
APIC0:1
VDD_PCI
PCIF0:1
2
PCI0:5
PCI_STP#
Fract.
Aligner
VDD_AGP
AGP0:1
PLL2
PD#
VDD_48
48 MHz
24_48MHz
2
VDD_REF
**FS0/REF0
**FS1/REF1
REF2
GND_REF
XIN
XOUT
GND_Z
ZCLK0
ZCLK1
VDD_Z
*PCI_STP#
VDD_PCI
**FS2/PCIF0
*FS3/PCIF1
PCI0
PCI1
GND_PCI
VDD_PCI
PCI2
PCI3
PCI4
PCI5
GND_PCI
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
48
47
46
45
44
43
42
41
40
39
38
37
36
35
34
33
32
31
30
29
28
27
26
25
VDD_APIC
IOAPIC1
IOAPIC0
GND_APIC
CPU_STP#*
CPUT1
VDD_CPU
GND_CPU
CPUT0
CPUC0
VDD_CPU
GNDA
VDDA
SCLK
SDATA
PD#*
GND_AGP
AGP0
AGP1
VDD_AGP
VDD_48
48MHZ
24_48MHZ
GND_48
~
SDATA
SCLK
I2C
Logic
SSOP-48
* : Internal Pull-up 150k
** : Internal Pull-down 150k
CY28372
Rev 1.0, November 20, 2006
2200 Laurelwood Road, Santa Clara, CA 95054
Tel:(408) 855-0555
Fax:(408) 855-0550
Page 1 of 17
www.SpectraLinear.com
CY28372
Pin Description
Pin #.
6
Name
XIN
Type
I
Description
Crystal Connection or External Reference Frequency Input.
This pin has dual
functions. It can be used as an external 14.318-MHz crystal connection or as an
external reference frequency input.
Crystal Connection.
Connection for an external 14.318-MHz crystal. If using an
external reference, this pin must be left unconnected.
Reference Clock.
14.31818 reference outputs.
Reference Clock.
14.31818 reference outputs.
Frequency Select.
Sampled upon power-on to determine device operating frequency.
Free-running PCI.
Independent of PCI_STP#.
Frequency Select.
Sampled upon power-on to determine device operating frequency.
PCI Clock.
PCI Stop.
Stops all PCI clocks
Differential CPU Outputs.
“True”
Clock of Differential CPU Outputs.
For chipset host bus
CPU Stop.
Stops all CPU clocks
MuTIOL Clock Outputs.
IOAPIC.
2.5 V clock outputs
48 MHz Clock.
USB clock outputs
24 MHz or 48 MHz Clock.
Selectable SIO clock outputs. Default output frequency is
24 MHz, but can be configured for 48 MHz through I
2
C.
AGP Clock.
I
2
C Data.
5v tolerant
I
2
C Clock.5v
tolerant
Power-down Control.
Turns off all clock outputs and shuts down device
3.3V Analog Power/Ground.
Power supply for core logic, PLL circuitry
3.3V Power and Ground.
Power supply for respective output buffers.
7
4
2, 3
14, 15
16, 17, 20,
21, 22, 23
12
40
39
43
44
9, 10
46, 47
27
26
31, 30
34
35
33
36
37
1, 5, 8, 11,
13, 18, 19,
24, 25, 28,
29, 32
XOUT
REF2
REF[0:1]/
FS[0:1]
PCIF[0:1]/
FS[2:3]
PCI [0:5]
PCI_STP#
CPUT0
CPUC0
CPUT1
CPU_STP#
ZCLK[0:1]
IOAPIC[0:1]
48MHz
24_48MHz
AGP[0:1]
SDATA
SCLK
PD#
VDDA
GNDA
VDD_REF,
GND_REF,
GND_Z,
VDD_Z,
VDD_PCI,
GND_PCI,
GND_48,
VDD_48,
VDD_AGP,
GND_AGP
VDD_CPU,
GND_CPU,
VDD_APIC,
GND_APIC
O
O
O
I
O
I
O
I
O
O
I
O
O
O
O
O
I/O
I
I
PWR
PWR
PWR
38, 41, 42
48, 45
PWR
2.5V Power and Ground.
Power supply for respective output buffers.
Rev 1.0, November 20, 2006
Page 2 of 17
CY28372
Table 1. Frequency Selection Table
Input Conditions
Option
(byte 4, bit 2)
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
(default)
I
2
C
FS(3:0)
0000
0001
0010
0011
0100
0101
0110
0111
1000
1001
1010
1011
1100
1101
1110
1111
0000
0001
0010
0011
0100
0101
0110
0111
1000
1001
1010
1011
1100
1101
1110
1111
CPU
(MHz)
133.3
133.3
133.3
133.3
133.3
133.3
133.3
133.3
100.0
100.0
100.0
100.0
100.0
100.0
111.0
111.0
114.5
120.0
133.3
133.3
133.3
145.7
150.0
166.6
111.1
137.4
144.9
150.0
155.1
166.6
180.1
200.0
Output Frequency
ZCLK
(MHz)
66.7
66.7
100.0
100.0
133.3
133.3
166.6
166.6
66.7
66.7
100.0
100.0
133.3
133.3
166.5
166.5
95.4
100.0
83.3
111.1
133.3
116.6
100.0
111.1
133.3
137.4
144.9
150.0
124.1
133.3
135.1
133.3
AGP
(MHz)
66.7
50.0
66.7
50.0
66.7
50.0
66.7
55.5
66.7
50.0
66.7
50.0
66.7
50.0
66.6
55.5
63.6
66.7
66.7
74.1
83.3
64.8
66.7
66.7
66.7
68.7
64.4
66.7
68.9
66.7
67.6
66.7
PCI
(MHz)
33.3
33.3
33.3
33.3
33.3
33.3
33.3
33.3
33.3
33.3
33.3
33.3
33.3
33.3
33.3
33.3
31.8
33.3
33.3
33.3
33.3
32.4
33.3
33.3
33.3
34.4
32.2
33.3
34.5
33.3
33.8
33.3
VCO
Freq.
(MHz)
400.0
400.0
400.0
400.0
400.0
400.0
666.5
666.5
400.0
400.0
400.0
400.0
400.0
400.0
666.1
666.1
572.5
600.0
666.5
666.5
666.5
582.8
600.0
666.5
666.5
549.6
579.5
600.0
620.3
666.5
540.4
400.0
Serial Data Interface
To enhance the flexibility and function of the clock synthesizer,
a two-signal serial interface is provided. Through the Serial
Data Interface, various device functions, such as individual
clock output buffers, can be individually enabled or disabled.
The registers associated with the Serial Data Interface
initializes to their default setting upon power-up, and therefore
use of this interface is optional. Clock device register changes
are normally made upon system initialization, if any are
required. The interface can also be used during system
operation for power management functions.
Data Protocol
The clock driver serial protocol accepts byte write, byte read,
block write, and block read operations from the controller. For
block write/read operation, the bytes must be accessed in
sequential order from lowest to highest byte (most significant
bit first) with the ability to stop after any complete byte has
been transferred. For byte write and byte read operations, the
system controller can access individually indexed bytes. The
offset of the indexed byte is encoded in the command code,
as described in
Table 2.
Rev 1.0, November 20, 2006
Page 3 of 17
CY28372
The block write and block read protocol is outlined in
Table 3
while
Table 4
outlines the corresponding byte write and byte
read protocol. The slave receiver address is 11010010 (D2h).
Table 2. Command Code Definition
Bit
7
(6:0)
Description
0 = Block read or block write operation, 1 = Byte
read or byte write operation
Byte offset for byte read or byte write operation.
For block read or block write operations, these bits
should be '0000000'
Table 3. Block Read and Block Write Protocol
Block Write Protocol
Bit
1
2:8
9
10
11:18
19
20:27
28
29:36
37
38:45
46
....
....
....
....
....
....
Start
Slave address – 7 bits
Write = 0
Acknowledge from slave
Command Code – 8 bits
'00000000' stands for block operation
Acknowledge from slave
Byte Count – 8 bits
Acknowledge from slave
Data byte 1 – 8 bits
Acknowledge from slave
Data byte 2 – 8 bits
Acknowledge from slave
......................
Data Byte (N–1) –8 bits
Acknowledge from slave
Data Byte N –8 bits
Acknowledge from slave
Stop
Description
Bit
1
2:8
9
10
11:18
19
20
21:27
28
29
30:37
38
39:46
47
48:55
56
....
....
....
....
Table 4. Byte Read and Byte Write Protocol
Byte Write Protocol
Bit
1
2:8
9
10
11:18
Start
Slave address – 7 bits
Write = 0
Acknowledge from slave
Command Code – 8 bits
'1xxxxxxx' stands for byte operation, bits[6:0] of the
command code represents the offset of the byte to
be accessed
Acknowledge from slave
Data byte from master – 8 bits
Description
Bit
1
2:8
9
10
11:18
Start
Slave address – 7 bits
Write = 0
Acknowledge from slave
Command Code – 8 bits
'1xxxxxxx' stands for byte operation, bits[6:0] of the
command code represents the offset of the byte to
be accessed
Acknowledge from slave
Repeat start
Byte Read Protocol
Description
Start
Slave address – 7 bits
Write = 0
Acknowledge from slave
Command Code – 8 bits
'00000000' stands for block operation
Acknowledge from slave
Repeat start
Slave address – 7 bits
Read = 1
Acknowledge from slave
Byte count from slave – 8 bits
Acknowledge
Data byte from slave – 8 bits
Acknowledge
Data byte from slave – 8 bits
Acknowledge
Data bytes from slave/Acknowledge
Data byte N from slave – 8 bits
Not Acknowledge
Stop
Block Read Protocol
Description
19
20:27
19
20
Rev 1.0, November 20, 2006
Page 4 of 17
CY28372
Table 4. Byte Read and Byte Write Protocol
(continued)
Byte Write Protocol
Bit
28
29
Stop
Description
Acknowledge from slave
Bit
21:27
28
29
30:37
38
39
Read = 1
Acknowledge from slave
Data byte from slave – 8 bits
Not Acknowledge
Stop
Byte Read Protocol
Description
Slave address – 7 bits
Device Configuration Map
Data Bytes 0 to 3: Reserved for ZDB Registers
Byte 4
Bit
Bit 7
Bit 6
Bit 5
Bit 4
@Pup
1
0
0
0
Name
Frequency Select Register
(FS3)
Frequency Select Register
(FS2)
Frequency Select Register
(FS1)
Frequency Select Register
(FS0)
[7..4]
Bit2 = 0
0000
0001
0010
0011
0100
0101
0110
0111
1000
1001
1010
1011
1100
1101
1110
1111
Bit2 = 1
0000
0001
0010
0011
0100
0101
0110
0111
1000
1001
1010
1011
1100
1101
1110
1111
114.5
120.0
133.3
133.3
133.3
145.7
150.0
166.6
111.1
137.4
144.9
150.0
155.1
166.6
180.1
200.0
95.4
100.0
83.3
111.1
133.3
116.6
100.0
111.1
133.3
137.4
144.9
150.0
124.1
133.3
135.1
133.3
63.631.8
66.733.3
66.733.3
74.133.3
83.333.3
64.832.4
66.733.3
66.733.3
66.733.3
68.734.4
64.432.2
66.733.3
68.934.5
66.733.3
67.633.8
66.733.3
133.3
133.3
133.3
133.3
133.3
133.3
133.3
133.3
100.0
100.0
100.0
100.0
100.0
100.0
111.0
111.0
66.7
66.7
100.0
100.0
133.3
133.3
166.6
166.6
66.7
66.7
100.0
100.0
133.3
133.3
166.5
166.5
66.733.3
50.033.3
66.733.3
50.033.3
66.733.3
50.033.3
66.733.3
55.533.3
66.733.3
50.033.3
66.733.3
50.033.3
66.733.3
50.033.3
66.633.3
55.533.3
Description
CPU
ZCLK
AGPPCI
Bit 3
0
FS_Override
Frequency Selection Source:
0 = Select through hardware strapping, latched inputs
1 = Select through I
2
C
0 = Normal, 1 = Spread Spectrum enable
0 = Normal, 1 = three-state all outputs
Bit 2
Bit 1
Bit 0
Byte 5
Bit
Bit 7
Bit 6
Bit 5
Bit 4
0
1
0
Frequency Select Register Most significant bit of I
2
C Frequency Select Register
Spread Spectrum Control
Output Disable
@Pup
0
0
0
0
Reserved
Reserved
Reserved
Reserved
Name
Reserved
Reserved
Reserved
Reserved
Description
Rev 1.0, November 20, 2006
Page 5 of 17
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