organized as 524,288 bits x 32-bit x 4-bank for improved
performance. The synchronous DRAMs achieve high-speed
data transfer using pipeline architecture. All inputs and
outputs signals refer to the rising edge of the clock input.
PIN
DESCRIPTIONS
Address Input
Bank Select Address
Data I/O
System Clock Input
Clock Enable
Chip Select
Row Address Strobe Command
Column Address Strobe Command
Write Enable
VCCQ
I/O19
I/O20
GNDQ
I/O21
I/O22
VCCQ
I/O23
VCC
A0-A10
BA0, BA1
I/O0 to I/O31
CLK
CKE
CS
RAS
CAS
WE
Vcc
GND
Vcc
Q
GND
Q
NC
Power
Ground
Power Supply for I/O Pin
Ground for I/O Pin
No Connection
DQM0 to DQM3 Input/Output Mask
This document contains ADVANCE INFORMATION data. ISSI reserves the right to make changes to its products at any time without notice in order to improve design and supply the best
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