EEWORLDEEWORLDEEWORLD

Part Number

Search

64MD-45-800

Description
Rambus DRAM, 4MX16, 45ns, CMOS, PBGA74, BGA-74
Categorystorage    storage   
File Size3MB,66 Pages
ManufacturerRambus Inc
Download Datasheet Parametric Compare View All

64MD-45-800 Overview

Rambus DRAM, 4MX16, 45ns, CMOS, PBGA74, BGA-74

64MD-45-800 Parametric

Parameter NameAttribute value
MakerRambus Inc
Parts packaging codeBGA
package instruction,
Contacts74
Reach Compliance Codeunknown
ECCN codeEAR99
access modeBLOCK ORIENTED PROTOCOL
Maximum access time45 ns
JESD-30 codeR-PBGA-B74
memory density67108864 bit
Memory IC TypeRAMBUS DRAM
memory width16
Number of functions1
Number of ports1
Number of terminals74
word count4194304 words
character code4000000
Operating modeSYNCHRONOUS
organize4MX16
Package body materialPLASTIC/EPOXY
Package shapeRECTANGULAR
Package formGRID ARRAY
Certification statusNot Qualified
Maximum supply voltage (Vsup)2.63 V
Minimum supply voltage (Vsup)2.37 V
Nominal supply voltage (Vsup)2.5 V
surface mountYES
technologyCMOS
Terminal formBALL
Terminal locationBOTTOM
Direct RDRAM
®
RAMBUS
Preliminary Information
64/72-Mbit (256Kx16/18x16d)
Overview
The Rambus Direct RDRAM™ is a general purpose
high-performance memory device suitable for use in a
broad range of applications including computer
memory, graphics, video, and any other application
where high bandwidth and low latency are required.
The 64/72-Mbit Direct Rambus DRAMs (RDRAM
)
are extremely high-speed CMOS DRAMs organized as
4M words by 16 or 18 bits. The use of Rambus
Signaling Level (RSL) technology permits 600MHz to
800MHz transfer rates while using conventional
system and board design technologies. Direct RDRAM
devices are capable of sustained data transfers at 1.25
ns per two bytes (10ns per sixteen bytes).
The architecture of the Direct RDRAMs allows the
highest sustained bandwidth for multiple, simulta-
neous randomly addressed memory transactions. The
separate control and data buses with independent row
and column control yield over 95% bus efficiency. The
Direct RDRAM's 16 banks support up to four simulta-
neous transactions.
System oriented features for mobile, graphics and large
memory systems include power management, byte
masking, and x18 organization. The two data bits in the
x18 organization are general and can be used for addi-
tional storage and bandwidth or for error correction.
Figure 1: Direct RDRAM CSP Package
The 64/72-Mbit Direct RDRAMs are offered in a CSP
horizontal package suitable for desktop as well as low-
profile add-in card and mobile applications.
Key Timing Parameters/Part Numbers
Organization
a
256Kx16x16d
256Kx16x16d
I/O Freq. Core Access Time
MHz
(ns)
600
711
711
800
800
600
711
711
800
800
53
50
45
45
40
53
50
45
45
40
Part
Number
64MD-53-600
64MD-50-711
64MD-45-711
64MD-45-800
64MD-40-800
72MD-53-600
72MD-50-711
72MD-45-711
72MD-45-800
72MD-40-800
Features
s
Highest sustained bandwidth per DRAM device
- 1.6GB/s sustained data transfer rate
- Separate control and data buses for maximized
efficiency
- Separate row and column control buses for
easy scheduling and highest performance
- 16 banks: four transactions can take place simul-
taneously at full bandwidth data rates
Low latency features
- Write buffer to reduce read latency
- 3 precharge mechanisms for controller flexibility
- Interleaved transactions
Advanced power management:
- Multiple low power states allows flexibility in
power consumption versus time to transition to
active state
- Power-down self-refresh
Organization: 1Kbyte pages and 16 banks, x 16/18
- x18 organization allows ECC configurations or
increased storage/bandwidth
- x16 organization for low cost applications
Uses Rambus Signaling Level (RSL) for up to
800MHz operation
256Kx16x16d
256Kx16x16d
256Kx16x16d
256Kx18x16d
256Kx18x16d
256Kx18x16d
256Kx18x16d
256Kx18x16d
s
a. The “16d” designation indicates that this RDRAM core is com-
posed of 16 banks which use a “doubled” bank architecture.
s
Related Documentation
Data sheets for the Rambus memory system compo-
nents, including the RIMM module, RIMM connector,
and clock generator, are available on the Rambus
website at http://www.rambus.com.
s
s
Document DL0035
Version 1.1
Preliminary Information
Page 1

64MD-45-800 Related Products

64MD-45-800 64MD-50-711 72MD-50-711 72MD-45-711 64MD-40-800 64MD-45-711 64MD-53-600 72MD-40-800 72MD-53-600 72MD-45-800
Description Rambus DRAM, 4MX16, 45ns, CMOS, PBGA74, BGA-74 Rambus DRAM, 4MX16, CMOS, PBGA74, BGA-74 Rambus DRAM, 4MX18, CMOS, PBGA54, CENTER BONDED, BGA-54 Rambus DRAM, 4MX18, CMOS, PBGA54, CENTER BONDED, BGA-54 Rambus DRAM, 4MX16, 40ns, CMOS, PBGA74, BGA-74 Rambus DRAM, 4MX16, CMOS, PBGA74, BGA-74 Rambus DRAM, 4MX16, 53ns, CMOS, PBGA74, BGA-74 Rambus DRAM, 4MX18, 40ns, CMOS, PBGA54, CENTER BONDED, BGA-54 Rambus DRAM, 4MX18, 53ns, CMOS, PBGA54, CENTER BONDED, BGA-54 Rambus DRAM, 4MX18, 45ns, CMOS, PBGA54, CENTER BONDED, BGA-54
Maker Rambus Inc Rambus Inc Rambus Inc Rambus Inc Rambus Inc Rambus Inc Rambus Inc Rambus Inc Rambus Inc Rambus Inc
Parts packaging code BGA BGA BGA BGA BGA BGA BGA BGA BGA BGA
Contacts 74 74 54 54 74 74 74 54 54 54
Reach Compliance Code unknown unknown unknown unknown unknown unknown unknown unknown unknown unknow
ECCN code EAR99 EAR99 EAR99 EAR99 EAR99 EAR99 EAR99 EAR99 EAR99 EAR99
access mode BLOCK ORIENTED PROTOCOL BLOCK ORIENTED PROTOCOL BLOCK ORIENTED PROTOCOL BLOCK ORIENTED PROTOCOL BLOCK ORIENTED PROTOCOL BLOCK ORIENTED PROTOCOL BLOCK ORIENTED PROTOCOL BLOCK ORIENTED PROTOCOL BLOCK ORIENTED PROTOCOL BLOCK ORIENTED PROTOCOL
JESD-30 code R-PBGA-B74 R-PBGA-B74 R-PBGA-B54 R-PBGA-B54 R-PBGA-B74 R-PBGA-B74 R-PBGA-B74 R-PBGA-B54 R-PBGA-B54 R-PBGA-B54
memory density 67108864 bit 67108864 bit 75497472 bit 75497472 bit 67108864 bit 67108864 bit 67108864 bit 75497472 bit 75497472 bit 75497472 bi
Memory IC Type RAMBUS DRAM RAMBUS DRAM RAMBUS DRAM RAMBUS DRAM RAMBUS DRAM RAMBUS DRAM RAMBUS DRAM RAMBUS DRAM RAMBUS DRAM RAMBUS DRAM
memory width 16 16 18 18 16 16 16 18 18 18
Number of functions 1 1 1 1 1 1 1 1 1 1
Number of ports 1 1 1 1 1 1 1 1 1 1
Number of terminals 74 74 54 54 74 74 74 54 54 54
word count 4194304 words 4194304 words 4194304 words 4194304 words 4194304 words 4194304 words 4194304 words 4194304 words 4194304 words 4194304 words
character code 4000000 4000000 4000000 4000000 4000000 4000000 4000000 4000000 4000000 4000000
Operating mode SYNCHRONOUS SYNCHRONOUS SYNCHRONOUS SYNCHRONOUS SYNCHRONOUS SYNCHRONOUS SYNCHRONOUS SYNCHRONOUS SYNCHRONOUS SYNCHRONOUS
organize 4MX16 4MX16 4MX18 4MX18 4MX16 4MX16 4MX16 4MX18 4MX18 4MX18
Package body material PLASTIC/EPOXY PLASTIC/EPOXY PLASTIC/EPOXY PLASTIC/EPOXY PLASTIC/EPOXY PLASTIC/EPOXY PLASTIC/EPOXY PLASTIC/EPOXY PLASTIC/EPOXY PLASTIC/EPOXY
Package shape RECTANGULAR RECTANGULAR RECTANGULAR RECTANGULAR RECTANGULAR RECTANGULAR RECTANGULAR RECTANGULAR RECTANGULAR RECTANGULAR
Package form GRID ARRAY GRID ARRAY GRID ARRAY GRID ARRAY GRID ARRAY GRID ARRAY GRID ARRAY GRID ARRAY GRID ARRAY GRID ARRAY
Certification status Not Qualified Not Qualified Not Qualified Not Qualified Not Qualified Not Qualified Not Qualified Not Qualified Not Qualified Not Qualified
Maximum supply voltage (Vsup) 2.63 V 2.63 V 2.63 V 2.63 V 2.63 V 2.63 V 2.63 V 2.63 V 2.63 V 2.63 V
Minimum supply voltage (Vsup) 2.37 V 2.37 V 2.37 V 2.37 V 2.37 V 2.37 V 2.37 V 2.37 V 2.37 V 2.37 V
Nominal supply voltage (Vsup) 2.5 V 2.5 V 2.5 V 2.5 V 2.5 V 2.5 V 2.5 V 2.5 V 2.5 V 2.5 V
surface mount YES YES YES YES YES YES YES YES YES YES
technology CMOS CMOS CMOS CMOS CMOS CMOS CMOS CMOS CMOS CMOS
Terminal form BALL BALL BALL BALL BALL BALL BALL BALL BALL BALL
Terminal location BOTTOM BOTTOM BOTTOM BOTTOM BOTTOM BOTTOM BOTTOM BOTTOM BOTTOM BOTTOM
Maximum access time 45 ns - - - 40 ns - 53 ns 40 ns 53 ns 45 ns
The circuit is heating up. Please help analyze the circuit.
[i=s]This post was last edited by kal9623287 on 2022-8-8 09:32[/i]The circuit below is not complicated, but I just can't figure it out. When D2, D3, and D4 are turned on, U1 and U2 heat up very badly,...
kal9623287 Power technology
5 STM32F103C8
I found an STM32F103C8. It was absolutely genuine when I bought it, but I bought it in 2018. I wonder if anyone wants it now? If so, how much would you offer?...
呜呼哀哉 Buy&Sell
MSP432 learning experience: system tick timer
The system tick timer is very important in the operating system. It can provide a good system clock beat, just like our heart, beating at a certain frequency. It provides a good time base for the oper...
灞波儿奔 Microcontroller MCU
Verilog basic syntax task
I have never used the task syntax, and I was worried that it was not synthesizable, so I didn't try it. I practiced it recently and felt that it was quite easy to use. I would like to share it with yo...
chenzhufly FPGA/CPLD
Watchdog Timer
Why can the watchdog timer work when WDTCTL = WDTPW+WDTSSEL + WDTTMSEL + WDTCNTCL are configured at the same time, but the watchdog timer does not work when WDTCTL = WDTPW; WDTCTL |= |WDTSSEL + WDTTMS...
赵俊阳 Microcontroller MCU
Some experience with parallel FLASH booting
Some experience in parallel FLASH booting Recently, the discussion about FLASH and BOOT on BBS has been very active, and I have come here many times to ask for advice. A few days ago, the homemade DSP...
xiangzi MCU

EEWorld
subscription
account

EEWorld
service
account

Automotive
development
circle

Robot
development
community

Index Files: 1178  1304  2366  1034  1246  24  27  48  21  26 
Datasheet   0 1 2 3 4 5 6 7 8 9 A B C D E F G H I J K L M N O P Q R S T U V W X Y Z
Room 1530, 15th Floor, Building B, No. 18 Zhongguancun Street, Haidian District, Beijing Telephone: (010) 82350740 Postal Code: 100190
Copyright © 2005-2026 EEWORLD.com.cn, Inc. All rights reserved 京ICP证060456号 京ICP备10001474号-1 电信业务审批[2006]字第258号函 京公网安备 11010802033920号