Direct RDRAM
™
®
RAMBUS
Preliminary Information
64/72-Mbit (256Kx16/18x16d)
Overview
The Rambus Direct RDRAM™ is a general purpose
high-performance memory device suitable for use in a
broad range of applications including computer
memory, graphics, video, and any other application
where high bandwidth and low latency are required.
The 64/72-Mbit Direct Rambus DRAMs (RDRAM
)
are extremely high-speed CMOS DRAMs organized as
4M words by 16 or 18 bits. The use of Rambus
Signaling Level (RSL) technology permits 600MHz to
800MHz transfer rates while using conventional
system and board design technologies. Direct RDRAM
devices are capable of sustained data transfers at 1.25
ns per two bytes (10ns per sixteen bytes).
The architecture of the Direct RDRAMs allows the
highest sustained bandwidth for multiple, simulta-
neous randomly addressed memory transactions. The
separate control and data buses with independent row
and column control yield over 95% bus efficiency. The
Direct RDRAM's 16 banks support up to four simulta-
neous transactions.
System oriented features for mobile, graphics and large
memory systems include power management, byte
masking, and x18 organization. The two data bits in the
x18 organization are general and can be used for addi-
tional storage and bandwidth or for error correction.
Figure 1: Direct RDRAM CSP Package
The 64/72-Mbit Direct RDRAMs are offered in a CSP
horizontal package suitable for desktop as well as low-
profile add-in card and mobile applications.
Key Timing Parameters/Part Numbers
Organization
a
256Kx16x16d
256Kx16x16d
I/O Freq. Core Access Time
MHz
(ns)
600
711
711
800
800
600
711
711
800
800
53
50
45
45
40
53
50
45
45
40
Part
Number
64MD-53-600
64MD-50-711
64MD-45-711
64MD-45-800
64MD-40-800
72MD-53-600
72MD-50-711
72MD-45-711
72MD-45-800
72MD-40-800
Features
s
Highest sustained bandwidth per DRAM device
- 1.6GB/s sustained data transfer rate
- Separate control and data buses for maximized
efficiency
- Separate row and column control buses for
easy scheduling and highest performance
- 16 banks: four transactions can take place simul-
taneously at full bandwidth data rates
Low latency features
- Write buffer to reduce read latency
- 3 precharge mechanisms for controller flexibility
- Interleaved transactions
Advanced power management:
- Multiple low power states allows flexibility in
power consumption versus time to transition to
active state
- Power-down self-refresh
Organization: 1Kbyte pages and 16 banks, x 16/18
- x18 organization allows ECC configurations or
increased storage/bandwidth
- x16 organization for low cost applications
Uses Rambus Signaling Level (RSL) for up to
800MHz operation
256Kx16x16d
256Kx16x16d
256Kx16x16d
256Kx18x16d
256Kx18x16d
256Kx18x16d
256Kx18x16d
256Kx18x16d
s
a. The “16d” designation indicates that this RDRAM core is com-
posed of 16 banks which use a “doubled” bank architecture.
s
Related Documentation
Data sheets for the Rambus memory system compo-
nents, including the RIMM module, RIMM connector,
and clock generator, are available on the Rambus
website at http://www.rambus.com.
s
s
Document DL0035
Version 1.1
Preliminary Information
Page 1
Direct RDRAM™ 64/72-Mbit (256Kx16/18x16d)
Pinouts and Definitions
Edge-Bonded Devices
This table shows the pin assignments of the edge-
bonded RDRAM package from the top-side of the
package (the view looking down on the package as it is
mounted on the circuit board). The mechanical dimen-
sions of this package are shown in a later section. Refer
to Section "Edge-Bonded uBGA Package" on page 62.
Note - pin #1 is at the A1 position. .
Table 1: Edge-Bonded Device (top view)
7
6
5
4
3
2
1
A
B
C
VDD
D
GND
E
VDD
F
GND
G
H
J
VDD
K
GND
L
VDD
M
GND
N
P
R
T
GND
DQA8
GND
DQA7
DQA6
VDD
DQA5
DQA4
GND
GND
DQA3
DQA2
VDD
VDD
DQA1
DQA0
VDD
SCK
GND
CFMN
CFM
GND
CMD
V-REF
CTMN
CTM
GNDa
VCMOS
VDD
RQ7
RQ6
GNDa
GND
GND
RQ5
RQ4
VDDa
GND
VDD
RQ3
RQ2
VDDa
VCMOS
GND
RQ1
RQ0
GND
SIO1
VDD
DQB1
DQB0
VDD
SIO0
GND
DQB3
DQB2
VDD
VDD
DQB5
DQB4
GND
GND
DQB7
DQB6
GND
DQB8
x16
x18
Center-Bonded Devices - Preliminary
This table shows the pin assignments of the center-
bonded RDRAM package from the top-side of the
package (the view looking down on the package as it is
mounted on the circuit board). The mechanical dimen-
sions of this package are shown in a later sectio. Refer
to Section "Center-Bonded uBGA Package" on page 63.
Note - pin #1 is at the A1 position.
Table 2: Center-Bonded Device (top view)
8
7
6
5
4
3
2
1
SCK
VCMOS
DQA8
DQA6
GND
DQA3
DQA1
VDD
DQA0
VREF
GND
CTMN
RQ7
GND
CTM
RQ1
VDD
RQ4
DQB2
GND
RQ0
DQB6
GND
DQB3
SIO0
VCMOS
DQB8
DQA7
GND
CMD
DQA4
VDD
DQA5
CFM
GND
DQA2
CFMN
GNDa
VDDa
RQ5
VDD
RQ6
RQ3
GND
RQ2
DQB0
VDD
DQB1
DQB4
VDD
DQB5
DQB7
GND
SIO1
A
B
C
D
E
F
G
H
J
Page 2
Preliminary Information
Document DL0035
Version 1.1
Direct RDRAM™ 64/72-Mbit (256Kx16/18x16d)
Table 3: Pin Description
Signal
SIO1,SIO0
I/O
I/O
Type
CMOS
a
# Pins
edge
2
# Pins
center
2
Description
Serial input/output. Pins for reading from and writing to the control
registers using a serial access protocol. Also used for power man-
agement.
Command input. Pins used in conjunction with SIO0 and SIO1 for
reading from and writing to the control registers. Also used for
power management.
Serial clock input. Clock source used for reading from and writing to
the control registers
Supply voltage for the RDRAM core and interface logic.
Supply voltage for the RDRAM analog circuitry.
Supply voltage for CMOS input/output pins.
Ground reference for RDRAM core and interface.
Ground reference for RDRAM analog circuitry.
Data byte A. Nine pins which carry a byte of read or write data
between the Channel and the RDRAM. DQA8 is not used by
RDRAMs with a x16 organization.
Clock from master. Interface clock used for receiving RSL signals
from the Channel. Positive polarity.
Clock from master. Interface clock used for receiving RSL signals
from the Channel. Negative polarity
Logic threshold reference voltage for RSL signals
Clock to master. Interface clock used for transmitting RSL signals
to the Channel. Negative polarity.
Clock to master. Interface clock used for transmitting RSL signals
to the Channel. Positive polarity.
Row access control. Three pins containing control and address
information for row accesses.
Column access control. Five pins containing control and address
information for column accesses.
Data byte B. Nine pins which carry a byte of read or write data
between the Channel and the RDRAM. DQB8 is not used by
RDRAMs with a x16 organization.
CMD
I
CMOS
a
1
1
SCK
V
DD
V
DDa
V
CMOS
GND
GNDa
DQA8..DQA0
I
CMOS
a
1
14
2
2
19
2
1
6
1
2
9
1
9
I/O
RSL
b
9
CFM
CFMN
V
REF
CTMN
CTM
RQ7..RQ5 or
ROW2..ROW0
RQ4..RQ0 or
COL4..COL0
DQB8..
DQB0
I
I
RSL
b
RSL
b
1
1
1
1
1
1
1
1
3
5
9
I
I
I
I
I/O
RSL
b
RSL
b
RSL
b
RSL
b
RSL
b
1
1
3
5
9
Total pin count per package
74
54
a. All CMOS signals are high-true; a high voltage is a logic one and a low voltage is logic zero.
b. All RSL signals are low-true; a low voltage is a logic one and a high voltage is logic zero.
Document DL0035
Version 1.1
Preliminary Information
Page 3
Direct RDRAM™ 64/72-Mbit (256Kx16/18x16d)
DQB8..DQB0
9
RQ7..RQ5 or
ROW2..ROW0
3
RCLK
1:8 Demux
CTM CTMN
SCK,CMD
2
SIO0,SIO1
2
CFM CFMN
RQ4..RQ0 or
COL4..COL0
5
DQA8..DQA0
9
RCLK
1:8 Demux
TCLK
RCLK
Control Registers
6
REFR
Power Modes
Packet Decode
ROWR
ROWA
11
5
4
9
ROP DR
AV
Match
COLX
5
4
DX
Packet Decode
COLC
5
5
4
6
BX COP DC
S
Match
COLM
8
8
C
MB MA
BR
R
DEVID
XOP
M
BC
Mux
Row Decode
Match
XOP Decode
DM
Write
Buffer
Mux
Mux
PRER
ACT
Sense Amp
32x72
SAmp SAmp SAmp SAmp SAmp SAmp SAmp SAmp SAmp SAmp SAmp SAmp SAmp SAmp SAmp SAmp SAmp
PREX
Column Decode & Mask
DRAM Core
32x72
0
512x64x144
Bank 0
0/1
32x72
72
SAmp SAmp SAmp SAmp SAmp SAmp SAmp SAmp SAmp SAmp SAmp SAmp SAmp SAmp SAmp SAmp SAmp
PREC
RD, WR
0
Internal DQB Data Path
72
72
Internal DQA Data Path
0/1
Bank 1
1/2
72
1/2
RCLK
2/3
9
9
Bank 2
9
9
RCLK
2/3
Bank 3
3/4
3/4
Bank 4
4/5
4/5
Write Buffer
Write Buffer
1:8 Demux
1:8 Demux
9
Bank 5
9
5/6
5/6
Bank 6
6/7
6/7
Bank 7
7/8
7/8
Bank 8
8/9
8/9
Bank 9
9/10
9/10 10/11 11/12 12/13 13/14 14/15
TCLK
9
9
TCLK
14/15 13/14 12/13 11/12 10/11
Bank 10
Bank 11
Bank 12
Bank 13
Bank 14
Bank 15
8:1 Mux
8:1 Mux
9
9
15
Figure 2: 64/74Mbit Direct RDRAM Block Diagram
15
Page 4
Preliminary Information
Document DL0035
Version 1.1
Direct RDRAM™ 64/72-Mbit (256Kx16/18x16d)
General Description
Figure 2 is a block diagram of the 64/72Mbit Direct
RDRAM. It consists of two major blocks: a “core” block
built from banks and sense amps similar to those
found in other types of DRAM, and a Direct Rambus
interface block which permits an external controller to
access this core at up to 1.6GB/s.
ROW Pins:
The principle use of these three pins is to
manage the transfer of data between the banks and the
sense amps of the RDRAM. These pins are de-multi-
plexed into a 24-bit ROWA (row-activate) or ROWR
(row-operation) packet.
COL Pins:
The principle use of these five pins is to
manage the transfer of data between the DQA/DQB
pins and the sense amps of the RDRAM. These pins are
de-multiplexed into a 23-bit COLC (column-operation)
packet and either a 17-bit COLM (mask) packet or a 17-
bit COLX (extended-operation) packet.
Control Registers:
The CMD, SCK, SIO0, and SIO1
pins appear in the upper center of Figure 2. They are
used to write and read a block of control registers.
These registers supply the RDRAM configuration
information to a controller and they select the oper-
ating modes of the device. The nine bit REFR value is
used for tracking the last refreshed row. Most impor-
tantly, the five bit DEVID specifies the device address
of the RDRAM on the Channel.
ACT Command:
An ACT (activate) command from
an ROWA packet causes one of the 512 rows of the
selected bank to be loaded to its associated sense amps
(two 256 byte sense amps for DQA and two for DQB).
PRER Command:
A PRER (precharge) command
from an ROWR packet causes the selected bank to
release its two associated sense amps, permitting a
different row in that bank to be activated, or permitting
adjacent banks to be activated.
Clocking:
The CTM and CTMN pins (Clock-To-
Master) generate TCLK (Transmit Clock), the internal
clock used to transmit read data. The CFM and CFMN
pins (Clock-From-Master) generate RCLK (Receive
Clock), the internal clock signal used to receive write
data and to receive the ROW and COL pins.
RD Command:
The RD (read) command causes one
of the 64 dualocts of one of the sense amps to be trans-
mitted on the DQA/DQB pins of the Channel.
DQA,DQB Pins:
These 18 pins carry read (Q) and
write (D) data across the Channel. They are multi-
plexed/de-multiplexed from/to two 72-bit data paths
(running at one-eighth the data frequency) inside the
RDRAM.
WR Command:
The WR (write) command causes a
dualoct received from the DQA/DQB data pins of the
Channel to be loaded into the write buffer. There is also
space in the write buffer for the BC bank address and C
column address information. The data in the write
buffer is automatically retired (written with optional
bytemask) to one of the 64 dualocts of one of the sense
amps during a subsequent COP command. A retire can
take place during a RD, WR, or NOCOP to another
device, or during a WR or NOCOP to the same device.
The write buffer will not retire during a RD to the same
device. The write buffer reduces the delay needed for
the internal DQA/DQB data path turn-around.
Banks:
The 8Mbyte core of the RDRAM is divided
into 16 0.5Mbyte banks, each organized as 512 rows,
with each row containing 64 dualocts, and each
dualoct containing 16 bytes. A dualoct is the smallest
unit of data that can be addressed.
Sense Amps:
The RDRAM contains 17 sense amps.
Each sense amp consists of 512 bytes of fast storage
(256 for DQA and 256 for DQB) and can hold one-half
of one row of one bank of the RDRAM. The sense amp
may hold any of the 512 half-rows of an associated
bank. However, each sense amp is shared between two
adjacent banks of the RDRAM (except for sense amps 0
and 15). This introduces the restriction that adjacent
banks may not be simultaneously accessed.
PREC Precharge:
The PREC, RDA and WRA
commands are similar to NOCOP, RD and WR, except
that a precharge operation is performed at the end of
the column operation. These commands provide a
second mechanism for performing precharge.
RQ Pins:
These pins carry control and address infor-
mation. They are broken into two groups. RQ7..RQ5
are also called ROW2..ROW0, and are used primarily
for controlling row accesses. RQ4..RQ0 are also called
COL4..COL0, and are used primarily for controlling
column accesses.
PREX Precharge:
After a RD command, or after a
WR command with no byte masking (M=0), a COLX
packet may be used to specify an extended operation
(XOP). The most important XOP command is PREX.
This command provides a third mechanism for
performing precharge.
Document DL0035
Version 1.1
Preliminary Information
Page 5
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