ICS387G-XX datasheet, PDF - EEWORLD Datasheet

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ICS387G-XX: DescriptionClock Generator, 200MHz, CMOS, PDSO16, TSSOP-16; CategoryThe embedded processor and controller Microcontrollers and processors; File Size72KB，5 Pages; ManufacturerIDT (Integrated Device Technology)

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ICS387G-XX Overview

Clock Generator, 200MHz, CMOS, PDSO16, TSSOP-16

ICS387G-XX Parametric

Parameter Name	Attribute value
Is it lead-free?	Contains lead
Is it Rohs certified?	incompatible
Maker	IDT (Integrated Device Technology)
Parts packaging code	TSSOP
package instruction	TSSOP,
Contacts	16
Reach Compliance Code	compliant
ECCN code	EAR99
JESD-30 code	R-PDSO-G16
JESD-609 code	e0
length	5 mm
Humidity sensitivity level	1
Number of terminals	16
Maximum operating temperature	70 °C
Minimum operating temperature
Maximum output clock frequency	200 MHz
Package body material	PLASTIC/EPOXY
encapsulated code	TSSOP
Package shape	RECTANGULAR
Package form	SMALL OUTLINE, THIN PROFILE, SHRINK PITCH
Peak Reflow Temperature (Celsius)	240
Master clock/crystal nominal frequency	50 MHz
Certification status	Not Qualified
Maximum seat height	1.2 mm
Maximum supply voltage	5.5 V
Minimum supply voltage	3.13 V
Nominal supply voltage	3.3 V
surface mount	YES
technology	CMOS
Temperature level	COMMERCIAL
Terminal surface	Tin/Lead (Sn/Pb)
Terminal form	GULL WING
Terminal pitch	0.65 mm
Terminal location	DUAL
Maximum time at peak reflow temperature	20
width	4.4 mm
uPs/uCs/peripheral integrated circuit type	CLOCK GENERATOR, OTHER

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PRELIMINARY INFORMATION

ICS387

Quad PLL Quick Turn Clock Synthesizer

Features

• Packaged as 16 pin TSSOP

• Quick turn frequency programming allows

samples as quickly as one day

• Up to 2 outputs can be low-skew

• Can include 8 selectable output frequencies

• Up to 3 reference outputs

• Replaces multiple crystals and oscillators

• Output frequencies up to 200 MHz at 3.3V

• Input crystal frequency of 5 - 27 MHz

• Input clock frequency of 2 - 50 MHz

• Duty cycle of 45/55

• Operating voltages of 3.3 V or 5 V

• Advanced, low power CMOS process

Description

The ICS387 QTClock™ generates up to 5 high quality,

high frequency clock outputs including a reference

from a low frequency crystal or clock input. It is designed

to replace crystals and crystal oscillators in most

electronic systems. The ICS387 contains a One Time

Programmable (OTP) ROM which is factory programmed

with PLL divider values to output a broad range of

frequencies up to 200 MHz, allowing customer

requests for different frequencies to be shipped in 1-3

days. Programming features include a selectable

frequency table and up to 2 low-skew outputs.

Using Phase-Locked-Loop (PLL) techniques, the

device runs from a standard fundamental mode,

inexpensive crystal, or clock. It can replace multiple

crystals and oscillators, saving board space and cost.

Block Diagram

S2:S0

OTP

ROM

with PLL

Divider

Values

PLLA

CLK1

Divide

Logic

and

Output

Control

CLK2

CLK3

CLK4

PLLD

PLLB

Crystal

or clock

input

PLLC

X1/ICLK

Crystal

Oscillator

CLK5

PDTS (all outputs and PLLs)

Capacitors are required with a crystal input.

MDS 387 A

Revision 050401

Integrated Circuit Systems, Inc. • 525 Race Street • San Jose • CA• 95126 •( 408) 295-9800 • www.icst.com

PRELIMINARY INFORMATION

ICS387

Quad PLL Quick Turn Clock Synthesizer

Device Configuration

The ICS387 QTClock provides the facility for up to 5 clock outputs. The outputs are derived from either the

reference input or from one of the 4 PLLs. All chip functions are controlled from an OTP ROM which has 3 input

control lines (S2, S1, S0), giving a total of 8 address locations. Each address location gives control of the following:

1) Each output can be turned off individually

2) The internal dividers for each PLL are controlled to generate any required frequency.

3) Each PLL can be turned off (powered down) individually.

4) The output divide and control logic can be configured to bring the appropriate clock to the correct pin.

5) Up to four low skew copies of the same clock can be enabled.

This chip architecture provides the user with unrivaled flexibility. For example, one of the input pins could be used

to control the power of the chip by shutting down PLLs and outputs when not used. The second and third could

be used to change the output clock frequencies.

The specification is complete when the ICS387 QTClock Order Form accompanies this data sheet. The order form

lists the input and CLK actual frequencies, as well as any other available options. This unique configuration is given

a two character alphanumeric programming code (ICS387-xx), which must be specified when referring to samples

or ordering parts.

Frequency Select Table

The ICS387 can be configured so that one PLL provides up to 8 frequency selections. For example, CPU

frequencies of 66.7 MHz, 100.0 MHz, 133.3 MHz, and 166.7 MHz could be included. This information should be

indicated on the Order Form when the ICS387 is initially defined.

External Components / Crystal Selection

The ICS387 requires a 0.01µF decoupling capacitor to be connected between VDD and GND on pins 5 and 6, and

another between pins 12 and 11. These must be connected close to the ICS387 to minimize lead inductance. No

external power supply filtering is required for this device. A 33

Ω

series terminating resistor can be used next to

each CLK pin. For a crystal input, a parallel resonant, fundamental mode crystal should be used. Crystal capacitors

must be connected from each of the pins X1 and X2 to Ground. The value (in pF) of these crystal caps should equal

(CL -6pf)*2, where CL is the crystal load capacitance in pF. As an example, for a crystal with 16 pF load capacitance,

each crystal capacitor would be 20 pF [(16 - 6pf)*2 = 20].

For a clock input, connect to X1/ICLK and leave X2 unconnected (no capacitors on either X1 or X2).

MDS 387 A

Revision 050401

Integrated Circuit Systems, Inc. • 525 Race Street • San Jose • CA• 95126 •( 408) 295-9800 • www.icst.com

ICS387G-XX Related Products

	ICS387G-XX	ICS387G-XXIT-LF	ICS387G-XXI-LF	ICS387G-XX-LF	ICS387G-XXT-LF	ICS387G-XXIT	ICS387G-XXI	ICS387G-XXT
Description	Clock Generator, 200MHz, CMOS, PDSO16, TSSOP-16	Clock Generator, 200MHz, CMOS, PDSO16, TSSOP-16	Clock Generator, 200MHz, CMOS, PDSO16, TSSOP-16	Clock Generator, 200MHz, CMOS, PDSO16, TSSOP-16	Clock Generator, 200MHz, CMOS, PDSO16, TSSOP-16	Clock Generator, 200MHz, CMOS, PDSO16, TSSOP-16	Clock Generator, 200MHz, CMOS, PDSO16, TSSOP-16	Clock Generator, 200MHz, CMOS, PDSO16, TSSOP-16
Is it lead-free?	Contains lead	Lead free	Lead free	Lead free	Lead free	Contains lead	Contains lead	Contains lead
Is it Rohs certified?	incompatible	conform to	conform to	conform to	conform to	incompatible	incompatible	incompatible
Maker	IDT (Integrated Device Technology)	IDT (Integrated Device Technology)	IDT (Integrated Device Technology)	IDT (Integrated Device Technology)	IDT (Integrated Device Technology)	IDT (Integrated Device Technology)	IDT (Integrated Device Technology)	IDT (Integrated Device Technology)
Parts packaging code	TSSOP	TSSOP	TSSOP	TSSOP	TSSOP	TSSOP	TSSOP	TSSOP
package instruction	TSSOP,	TSSOP,	TSSOP,	TSSOP,	TSSOP,	TSSOP,	TSSOP,	TSSOP,
Contacts	16	16	16	16	16	16	16	16
Reach Compliance Code	compliant	compliant	compliant	compliant	compliant	compliant	compliant	compliant
ECCN code	EAR99	EAR99	EAR99	EAR99	EAR99	EAR99	EAR99	EAR99
JESD-30 code	R-PDSO-G16	R-PDSO-G16	R-PDSO-G16	R-PDSO-G16	R-PDSO-G16	R-PDSO-G16	R-PDSO-G16	R-PDSO-G16
JESD-609 code	e0	e3	e3	e3	e3	e0	e0	e0
length	5 mm	5 mm	5 mm	5 mm	5 mm	5 mm	5 mm	5 mm
Number of terminals	16	16	16	16	16	16	16	16
Maximum operating temperature	70 °C	85 °C	85 °C	70 °C	70 °C	85 °C	85 °C	70 °C
Maximum output clock frequency	200 MHz	200 MHz	200 MHz	200 MHz	200 MHz	200 MHz	200 MHz	200 MHz
Package body material	PLASTIC/EPOXY	PLASTIC/EPOXY	PLASTIC/EPOXY	PLASTIC/EPOXY	PLASTIC/EPOXY	PLASTIC/EPOXY	PLASTIC/EPOXY	PLASTIC/EPOXY
encapsulated code	TSSOP	TSSOP	TSSOP	TSSOP	TSSOP	TSSOP	TSSOP	TSSOP
Package shape	RECTANGULAR	RECTANGULAR	RECTANGULAR	RECTANGULAR	RECTANGULAR	RECTANGULAR	RECTANGULAR	RECTANGULAR
Package form	SMALL OUTLINE, THIN PROFILE, SHRINK PITCH	SMALL OUTLINE, THIN PROFILE, SHRINK PITCH	SMALL OUTLINE, THIN PROFILE, SHRINK PITCH	SMALL OUTLINE, THIN PROFILE, SHRINK PITCH	SMALL OUTLINE, THIN PROFILE, SHRINK PITCH	SMALL OUTLINE, THIN PROFILE, SHRINK PITCH	SMALL OUTLINE, THIN PROFILE, SHRINK PITCH	SMALL OUTLINE, THIN PROFILE, SHRINK PITCH
Peak Reflow Temperature (Celsius)	240	260	260	260	260	240	240	240
Master clock/crystal nominal frequency	50 MHz	50 MHz	50 MHz	50 MHz	50 MHz	50 MHz	50 MHz	50 MHz
Certification status	Not Qualified	Not Qualified	Not Qualified	Not Qualified	Not Qualified	Not Qualified	Not Qualified	Not Qualified
Maximum seat height	1.2 mm	1.2 mm	1.2 mm	1.2 mm	1.2 mm	1.2 mm	1.2 mm	1.2 mm
Maximum supply voltage	5.5 V	5.5 V	5.5 V	5.5 V	5.5 V	5.5 V	5.5 V	5.5 V
Minimum supply voltage	3.13 V	3.13 V	3.13 V	3.13 V	3.13 V	3.13 V	3.13 V	3.13 V
Nominal supply voltage	3.3 V	3.3 V	3.3 V	3.3 V	3.3 V	3.3 V	3.3 V	3.3 V
surface mount	YES	YES	YES	YES	YES	YES	YES	YES
technology	CMOS	CMOS	CMOS	CMOS	CMOS	CMOS	CMOS	CMOS
Temperature level	COMMERCIAL	INDUSTRIAL	INDUSTRIAL	COMMERCIAL	COMMERCIAL	INDUSTRIAL	INDUSTRIAL	COMMERCIAL
Terminal surface	Tin/Lead (Sn/Pb)	Matte Tin (Sn)	Matte Tin (Sn)	Matte Tin (Sn)	Matte Tin (Sn)	Tin/Lead (Sn/Pb)	Tin/Lead (Sn/Pb)	Tin/Lead (Sn/Pb)
Terminal form	GULL WING	GULL WING	GULL WING	GULL WING	GULL WING	GULL WING	GULL WING	GULL WING
Terminal pitch	0.65 mm	0.65 mm	0.65 mm	0.65 mm	0.65 mm	0.65 mm	0.65 mm	0.65 mm
Terminal location	DUAL	DUAL	DUAL	DUAL	DUAL	DUAL	DUAL	DUAL
Maximum time at peak reflow temperature	20	30	30	30	30	20	20	20
width	4.4 mm	4.4 mm	4.4 mm	4.4 mm	4.4 mm	4.4 mm	4.4 mm	4.4 mm
uPs/uCs/peripheral integrated circuit type	CLOCK GENERATOR, OTHER	CLOCK GENERATOR, OTHER	CLOCK GENERATOR, OTHER	CLOCK GENERATOR, OTHER	CLOCK GENERATOR, OTHER	CLOCK GENERATOR, OTHER	CLOCK GENERATOR, OTHER	CLOCK GENERATOR, OTHER

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