Analog Input ............................................................ 0V to (+V
S
+ 300mV)
Logic Input ............................................................... 0V to (+V
S
+ 300mV)
Case Temperature ......................................................................... +100°C
Junction Temperature .................................................................... +150°C
Storage Temperature .................................................................... +125°C
External Top Reference Voltage (REFT) ................................. +3.4V max
External Bottom Reference Voltage (REFB) ............................ +1.1V min
NOTES: (1) Stresses above these ratings may cause permanent damage.
Exposure to absolute maximum conditions for extended periods may degrade
device reliability.
ELECTROSTATIC
DISCHARGE SENSITIVITY
This integrated circuit can be damaged by ESD. Texas Instru-
ments recommends that all integrated circuits be handled with
appropriate precautions. Failure to observe proper handling
and installation procedures can cause damage.
ESD damage can range from subtle performance degradation
to complete device failure. Precision integrated circuits may be
more susceptible to damage because very small parametric
changes could cause the device not to meet its published
specifications.
PACKAGE/ORDERING INFORMATION(1)
PACKAGE
DESIGNATOR
DW
SPECIFIED
TEMPERATURE
RANGE
–40°C to +85°C
PACKAGE
MARKING
ADS821U
ORDERING
NUMBER
ADS821U
ADS821U/1K
TRANSPORT
MEDIA, QUANTITY
Rails, 28
Tape and Reel, 1000
PRODUCT
ADS821
PACKAGE-LEAD
SO-8
"
"
"
"
"
NOTE: (1) For the most current package and ordering information, see the Package Option Addendum at the end of this document, or see the TI website at
www.ti.com.
ELECTRICAL CHARACTERISTICS
At T
A
= +25°C, V
S
= +5V, Sampling Rate = 40MHz, and with a 50% duty cycle clock having a 2ns rise-and-fall time, unless otherwise noted.
ADS821U
PARAMETER
RESOLUTION
Specified Temperature Range
ANALOG INPUT
Differential Full-Scale Input Range
Common-Mode Voltage
Analog Input Bandwidth (–3dB)
Small-Signal
Full-Power
Input Impedance
DIGITAL INPUT
Logic Family
Convert Command
ACCURACY
(2)
Gain Error
Gain Drift
Power-Supply Rejection of Gain
Input Offset Error
Power-Supply Rejection of Offset
CONVERSION CHARACTERISTICS
Sample Rate
Data Latency
DYNAMIC CHARACTERISTICS
Differential Linearity Error
f = 500kHz
f = 12MHz
No Missing Codes
Integral Linearity Error at f = 500kHz
Spurious-Free Dynamic Range (SFDR)
f = 500kHz (–1dBFS input)
f = 12MHz (–1dBFS input)
t
H
= 13ns
(3)
+25°C
0°C to +70°C
+25°C
0°C to +70°C
0°C to +70°C
0°C to +70°C
+25°C
Full
+25°C
Full
60
54
58
54
CONDITIONS
T
AMBIENT
TEMP
MIN
–40
+1.25
TYP
MAX
10
+85
+3.25
+2.25
400
65
1.25 || 4
TTL/HCT Compatible CMOS
Falling Edge
+25°C
Full
∆
+V
S
=
±5%
∆
+V
S
=
±5%
+25°C
Full
+25°C
10k
6.5
±0.6
±1.1
±85
0.01
±2.1
0.02
±1.5
±2.5
0.15
±3.5
0.15
40M
%
%
ppm/°C
%FSR/%
%
%FSR/%
Sample/s
Convert Cycle
UNITS
Bits
°C
V
V
MHz
MHz
MΩ || pF
–20dBFS
(1)
Input
0dBFS Input
+25°C
+25°C
Start Conversion
±0.5
±0.6
±0.5
±0.6
Tested
±0.5
70
67
63
62
±1.0
±1.0
±1.0
±1.0
±2.0
LSB
LSB
LSB
LSB
LSB
dBFS
dBFS
dBFS
dBFS
NOTES: (1) dBFS refers to dB below Full-Scale. (2) Percentage accuracies are referred to the internal A/D converter Full-Scale Range of 4Vp-p. (3) Refer to Timing
Diagram footnotes for the differential linearity performance conditions for the SO and SSOP packages. (4) IMD is referred to the larger of the two input signals.
If referred to the peak envelope signal (≈ 0dB), the intermodulation products will be 7dB lower. (5) Based on (SINAD – 1.76)/6.02. (6) No “rollover” of bits.
2
ADS821
www.ti.com
SBAS040B
ELECTRICAL CHARACTERISTICS
(Cont.)
At T
A
= +25°C, V
S
= +5V, Sampling Rate = 40MHz, and with a 50% duty cycle clock having a 2ns rise-and-fall time, unless otherwise noted.
ADS821U
PARAMETER
DYNAMIC CHARACTERISTICS (Cont.)
2-Tone Intermodulation Distortion (IMD)
(4)
f = 4.4MHz and 4.5MHz (–7dBFS each tone)
Signal-to-Noise Ratio (SNR)
f = 500kHz (–1dBFS input)
f = 12MHz (–1dBFS input)
Signal-to-(Noise + Distortion) (SINAD)
f = 500kHz (–1dBFS input)
f = 12MHz (–1dBFS input)
Differential Gain Error
Differential Phase Error
Degrees
Effective Bits
(5)
Aperture Delay Time
Aperture Jitter
ps rms
Over-Voltage Recovery Time
(6)
OUTPUTS
Logic Family
Logic Coding
Logic Levels
NTSC or PAL
CONDITIONS
TEMP
MIN
TYP
MAX
UNITS
+25°C
Full
+25°C
Full
+25°C
Full
+25°C
Full
+25°C
Full
+25°C
NTSC or PAL
+25°C
+25°C
+25°C
1.5x Full-Scale Input
+25°C
57
55
56
54
56
52
53
50
+25°C
–61
–60
59
59
58
58
58.5
58
57
56
0.5
0.1
9.3
2
7
2
TTL/HCT Compatible CMOS
SOB or BTC
dBc
dBc
dB
dB
dB
dB
dB
dB
dB
dB
%
f
IN
= 3.58MHz
Bits
ns
ns
Logic Selectable
Logic LOW,
C
L
= 15pF max
Logic HIGH,
C
L
= 15pF max
Full
Full
0
+2.5
20
2
+4.75
+5
76
78
380
390
0.4
+V
S
40
10
+5.25
88
90
440
450
75
V
V
ns
ns
V
mA
mA
mW
mW
°C/W
3-State Enable Time
3-State Disable Time
POWER-SUPPLY REQUIREMENTS
Supply Voltage: +V
S
Supply Current: +I
S
Power Consumption
Thermal Resistance,
θ
JA
Operating
Operating
Operating
Operating
Operating
Full
Full
+25°C
Full
+25°C
Full
NOTES: (1) dBFS refers to dB below Full Scale. (2) Percentage accuracies are referred to the internal A/D converter Full-Scale Range of 4Vp-p. (3) Refer to Timing
Diagram footnotes for the differential linearity performance conditions for the SO and SSOP packages. (4) IMD is referred to the larger of the two input signals.
If referred to the peak envelope signal (≈ 0dB), the intermodulation products will be 7dB lower. (5) Based on (SINAD – 1.76)/6.02. (6) No “rollover” of bits.
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