PACDN006
6-Channel ESD Protection
Array
Product Description
The PACDN006 is a diode array designed to provide six channels of
ESD protection for electronic components or subsystems. Each
channel consists of a pair of diodes that steer an ESD current pulse to
either the positive (V
P
) or negative (V
N
) supply. The PACDN006
protects against ESD pulses up to:
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8
kV contact discharge, per International Standard
IEC 61000−4−2
15
kV per Human Body Model MIL−STD−883, Method 3015
(based on a 100 pF capacitor discharging through a 1.5 kW
resistor)
This device is particularly well−suited for portable electronics
(e.g., cellular phones, PDAs, notebook computers) because of its
small package footprint, high ESD protection level, and low loading
capacitance. It is also suitable for protecting video output lines and I/O
ports in computers and peripherals and is ideal for a wide range of
consumer electronics products.
The PACDN006 is available with RoHS compliant lead−free
finishing.
Features
MSOP 8
MR SUFFIX
CASE 846AB
SOIC 8
SM SUFFIX
CASE 751BD
ELECTRICAL SCHEMATIC
8
7
6
5
V
P
V
N
Six Channels of ESD Protection
8
kV Contact,
15
kV Air ESD Protection per Channel
(IEC 61000−4−2 Standard)
15
kV of ESD Protection per Channel (HBM)
Low Loading Capacitance (3 pF Typical)
Low Leakage Current is Ideal for Battery−Powered Devices
Available in Miniature 8−Pin MSOP and 8−Pin SOIC Packages
These Devices are Pb−Free and are RoHS Compliant
Consumer Electronic Products
Cellular Phones
PDAs
Notebook Computers
Desktop PCs
Digital Cameras and Camcorders
VGA (Video) Port Protection for Desktop and Portable PCs
1
2
3
4
MARKING DIAGRAM
006R
PACDN 006SM
Applications
006R
= PACDN006MR
PACDN 006SM = PACDN006SM
ORDERING INFORMATION
Device
PACDN006MR
PACDN006SM
Package
MSOP 8
(Pb−Free)
SOIC 8
(Pb−Free)
Shipping
†
4000/Tape & Reel
2500/Tape & Reel
†For information on tape and reel specifications,
including part orientation and tape sizes, please
refer to our Tape and Reel Packaging Specification
Brochure, BRD8011/D.
Semiconductor Components Industries, LLC, 2011
October, 2011
−
Rev. 5
1
Publication Order Number:
PACDN006/D
PACDN006
TYPICAL APPLICATION CIRCUIT
V
CC
3
7
0.22
mF*
PACDN006
1 2 4
5 6
8
I/O Port
Buffers
Expansion
Connector
Handheld/PDA ESD Protection
* Decoupling capacitor must be placed as close as possible to Pin7.
PACKAGE / PINOUT DIAGRAMS
Top View
CH1
CH2
V
N
CH3
1
2
3
4
8
7
6
5
CH6
V
P
CH5
CH4
CH1
CH2
V
N
CH3
1
2
3
4
006R
Top View
PACDN 006SM
8
7
6
5
CH6
V
P
CH5
CH4
8−Pin MSOP−8
8−Pin SOIC−8
Table 1. PIN DESCRIPTIONS
Pin
1
2
3
4
5
6
7
8
Name
CH1
CH2
V
N
CH3
CH4
CH5
V
P
CH6
Type
I/O
I/O
GND
I/O
I/O
I/O
Supply
I/O
ESD Channel
ESD Channel
Negative Voltage Supply Rail or Ground Reference Rail
ESD Channel
ESD Channel
ESD Channel
Positive Voltage Supply Rail
ESD Channel
Description
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2
PACDN006
SPECIFICATIONS
Table 2. ABSOLUTE MAXIMUM RATINGS
Parameter
Supply Voltage (V
P
−
V
N
)
Diode Forward DC Current (Note 1)
Operating Temperature Range
Storage Temperature Range
DC Voltage at any Channel Input
Package Power Rating
Rating
6.0
20
−40
to +85
−65
to +150
(V
N
−
0.5) to (V
P
+ 0.5)
200
Units
V
mA
C
C
V
mW
Stresses exceeding Maximum Ratings may damage the device. Maximum Ratings are stress ratings only. Functional operation above the
Recommended Operating Conditions is not implied. Extended exposure to stresses above the Recommended Operating Conditions may affect
device reliability.
1. Only one diode conducting at a time.
Table 3. STANDARD OPERATING CONDITIONS
Parameter
Operating Temperature Range
Operating Supply Voltage (V
P
−
V
N
)
Rating
−40
to +85
0 to 5.5
Units
C
V
Table 4. ELECTRICAL OPERATING CHARACTERISTICS
(Note 1)
Symbol
I
P
V
F
I
LEAK
C
IN
V
ESD
Parameter
Supply Current
Diode Forward Voltage
Channel Leakage Current
Channel Input Capacitance
ESD Protection
Peak Discharge Voltage at any
Channel Input, in System
a) Human Body Model,
MIL−STD−883, Method 3015
b) Contact Discharge per
IEC 61000−4−2
c) Air Discharge per IEC 61000−4−2
Channel Clamp Voltage
Positive Transients
Negative Transients
@ 1 MHz, V
P
= 5 V,
V
N
= 0 V, V
IN
= 2.5 V
(Note 2)
(Note 3)
(Note 4)
(Note 4)
@ 15 kV ESD HBM
15
8
15
V
P
+ 13.0
V
N
−
13.0
V
Conditions
(V
P
−
V
N
) = 5.5 V
I
F
= 20 mA
0.65
0.1
3
Min
Typ
Max
10
0.95
1.0
5
Units
mA
V
mA
pF
kV
V
CL
1.
2.
3.
4.
All parameters specified at T
A
= 25C unless otherwise noted. V
P
= 5 V, V
N
= 0 V unless noted.
From I/O pins to V
P
or V
N
only. V
P
bypassed to V
N
with a 0.22
mF
ceramic capacitor (see Application Information for more details).
Human Body Model per MIL−STD−883, Method 3015, C
Discharge
= 100 pF, R
Discharge
= 1.5 kWV
P
= 5.0 V, V
N
grounded.
Standard IEC 61000−4−2 with C
Discharge
= 150 pF, R
Discharge
= 330
W,
V
P
= 5.0 V, V
N
grounded.
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3
PACDN006
PERFORMANCE INFORMATION
Input Capacitance vs. Input Voltage
Figure 1. Typical Variation of C
IN
vs. V
IN
(V
P
= 5 V, V
N
= 0 V, 0.1
mF
Chip Capacitor between V
P
and V
N
)
APPLICATION INFORMATION
Design Considerations
In order to realize the maximum protection against ESD pulses, care must be taken in the PCB layout to minimize parasitic
series inductances on the Supply/Ground rails as well as the signal trace segment between the signal input (typically
a connector) and the ESD protection device. Refer to Figure 2, which illustrates an example of a positive ESD pulse striking
an input channel. The parasitic series inductance back to the power supply is represented by L
1
and L
2
. The voltage V
CL
on
the line being protected is:
V
CL
+
Fwd Voltage Drop of D
1
)
V
SUPPLY
)
L
1
d(I
ESD
)
dt
)
L
2
d(I
ESD
)
dt
where I
ESD
is the ESD current pulse, and V
SUPPLY
is the positive supply voltage.
An ESD current pulse can rise from zero to its peak value in a very short time. As an example, a level 4 contact discharge
per the IEC61000−4−2 standard results in a current pulse that rises from zero to 30 Amps in 1 ns. Here d(I
ESD
)/dt can be
approximated by
DI
ESD
/Dt, or 30/(1x10
−9
). So just 10 nH of series inductance (L
1
and L
2
combined) will lead to a 300 V
increment in V
CL
!
Similarly for negative ESD pulses, parasitic series inductance from the V
N
pin to the ground rail will lead to drastically
increased negative voltage on the line being protected.
Another consideration is the output impedance of the power supply for fast transient currents. Most power supplies exhibit
a much higher output impedance to fast transient current spikes. In the V
CL
equation above, the V
SUPPLY
term, in reality, is
given by (V
DC
+ I
ESD
x R
OUT
), where V
DC
and R
OUT
are the nominal supply DC output voltage and effective output impedance
of the power supply respectively. As an example, a R
OUT
of 1
W
would result in a 10 V increment in V
CL
for a peak I
ESD
of
10 A.
If the inductances and resistance described above are close to zero, the rail−clamp ESD protection diodes will do a good job
of protection. However, since this is not possible in practical situations, a bypass capacitor must be used to absorb the very high
frequency ESD energy. So for any brand of rail−clamp ESD protection diodes, a bypass capacitor should be connected between
the V
P
pin of the diodes and the ground plane (V
N
pin of the diodes) as shown in the Application Circuit diagram below. A value
of 0.22
mF
is adequate for IEC−61000−4−2 level 4 contact discharge protection (8 kV). Ceramic chip capacitors mounted with
short printed circuit board traces are good choices for this application. Electrolytic capacitors should be avoided as they have
poor high frequency characteristics. For extra protection, connect a zener diode in parallel with the bypass capacitor to mitigate
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4
PACDN006
the effects of the parasitic series inductance inherent in the capacitor. The breakdown voltage of the zener diode should be
slightly higher than the maximum supply voltage.
As a general rule, the ESD Protection Array should be located as close as possible to the point of entry of expected
electrostatic discharges. The power supply bypass capacitor mentioned above should be as close to the V
P
pin of the Protection
Array as possible, with minimum PCB trace lengths to the power supply, ground planes and between the signal input and the
ESD device to minimize stray series inductance.
Additional Information
See also ON Semiconductor Application Notes AP209, “Design Considerations for ESD Protection” and AP219, “ESD
Protection for USB 2.0 Systems”.
L
2
V
P
POSITIVE SUPPLY RAIL
PATH OF ESD CURRENT PULSE I
ESD
D
1
L
1
CHANNEL
INPUT
20 A
0A
0.22
mF
LINE BEING
PROTECTED
D
2
ONE
CHANNEL
OF
PACDN006
V
CL
V
N
GROUND RAIL
Figure 2. Application of Positive ESD Pulse between Input Channel and Ground
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BEING
PROTECTED
CHASSIS GROUND
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