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MOTOROLA
s
by MC68020/D
SEMICONDUCTOR
TECHNICAL DATA
MC68020
Technical Summary
This document contains information on a new product. Specifications and information
herein are subect to change without notice
MOTOROLA
@MOTOROLA
INC., 1991
-
@
(Replaces
Rev.
4
BR243/D Rev. 3)
The main features
Object-Code
Addressing
of the MC68020 are as follows:
with Earlier M68000 Microprocessors
for Enhanced
Support
Bit-Oriented
of High-Level
Compatible
Mode Extensions
Languages
— i.e., Video
New Bit Field Data Type Accelerates
Graphics
Fast On-Chip Instruction
width
Applications
BUS Band-
*,\
*’X,l,
$J,$<,.
,,.’~
‘!,.1,’$:.
~,
+ts.,
Coprocessor Interface to Companion 32-Bit Peripherals — the MC6&%$and
MC68882 Floating-Point
Coprocessor
and the MC68851 pag,~$~[$~$rnory
,,~ .ji:
,,);,;:>:$s
\
,.&.\ ,}Y$,$$
Management
Unit
“’$<p
,
a,.:?.:+!J
$..
*t.,
Pipelined Architecture with High Degree of Internal Parallel?~x~$Allowing Mul-
,,,. ,:
:
.,.>
‘,‘.1.
9?,,
tiple Instructions To Be Executed Concurrently
3(\.~$\.
..\\,, .*#:,m*$,
i{> ,
Cache Speeds Instructions
and Improves
Bus Is Nonmulti@~~~#~ and Full 32-Bits
..;}, ,~,~
+,1$.\\
~~‘~t,~:,
Dynamic Bus Sizing Efficiently Suppotis 8-/l6-/&J@tttt Memories and Periph-
,, 1’<*,*
3
,.;,-~
~~:,.
erals
i:.>.{..!,,
:>\ -
,
~k,:i:k
‘..\
‘
\*,,,:>
Full
Support of Virtual Memory and Virtu$~i,~achine
${j:
~
,j;:
16 32-Bit General-Purpose
Two 32-Bit Supervisor
isters
Data an~~$d’~~ess Registers
.~,,,
Stack Poi@e~$ and Five Special-Purpose
+:$,
\<f,>,p..,v
**\.,,;;~b
., ,~h
-,$>1.
‘:<i.,.
High-Performance
Asynchronous
Control
Reg-
MC68020 TECHNICAL
DATA
MOTOROLA
INTRODUCTION
The MC68020 is a high-performance
32-bit microprocessor.
It is the first micro-
processor to evolve from a 16-bit machine to a full 32-bit machine that provides
32-bit address and data buses as well as 32-bit internal structures. Many tech-
niques were utilized to improve performance
and maintain compatibility
with
other processors of the M68000 Family. Among the improvements
are new
addressing modes that better support high-level language structures, an exi
panded instruction
set providing 32-bit operations for the limited case~..~~$~
supported by the MC68000 and the MC68010, and several new instruc,t~$q,$~to
support new data types. For special-purpose
applications,
when ~~$~~~’$ral-
purpose processor is not adequate, a coprocessor interface is pr~{~d$&.
,<;:*i?\$:
~,,
\ i ,)
:*;, ~~~
The MC68020 is a high-performance
microprocessor
imple~,~~t&Fin
HCMOS,
which allows CMOS and HMOS (high-density
NMOS) ~p~~$~$~ be combined
on the same device. CMOS structures are used wheu$,(%~~~d and low power
are required, and HMOS structures are used when %$&/rnum silicon area is
desired. This technology
enables the MC68020 t~’’~e’~ery fast, consume less
power (less than 1.5 W), and have a reasonab~w~$@ll die size.
>+:s’
~$
,,,,+:>
$ ~..
(Sk, ~
,,:. x,.’”
Figure 1 is a block diagram of the MC680#0. %he processor is divided into two
main sections: the bus controller andjk~bicromach
ine. This division reflects
Figure
1. Block Diagram
MOTOROLA
MC68020
TECHNICAL
DATA
The bus controller consists of the address and data pads and multiplexer
required to support dynamic bus sizing, a macro bus controller to schedule the
bus cycles on the basis of priority with two state machines (one to control the
bus cycles for operand accesses and the other to control the bus cycles for
instruction accesses), and the instruction cache with its associated control.
The micromachine consists of an execution unit, nanoROM and microROM
storage, an instruction decoder, an instruction pipe, and associated con~rol
sections. The execution unit consists of an address section, an operand ad,~~x
section, and a data section. Microcode control is provided by a modifi#d:}Wo-
Ievel store of microROM and nanoROM. Programmed logical array~~{:~$#S) are
used to provide instruction decode and sequencing information. ~$flfi~truction
pipe and other individual control sections provide the seco,~~$&Fdecode
of
instructions and generate the actual control signals that d~o’~e’’and interpret
,’~,:
,+.,,,
‘\
nanoROM and microROM information.
‘1:.
.:..
-,.,.t,***/,.
,,,.,..,
..,,
*1$: “.,*$’.
)<,.
,<,
t?w,
~\,+\.>+$:.
.x..~i..!..
. ..1:
.h.,,,
,i~~~r,.,.-
,,::?
PROGRAMMING
m@d~L
‘:L...~,
, .,,v
,..**;,
,,. ,
‘$’:.
~,:$..’’~i~,
$,,,.
As shown in the programming models (se,$fi~$res 2 and 3), the MC68020 has
16 32-bit general-purpose registers, a 3~$bi*:@rogram counter, two 32-bit super-
visor stack pointers, a 16-bit status rt~$~~~er, 32-bit vector base register, two
a
3-bit alternate function code regis$~$~~~nd two 32-bit cache handiing (address
and control) registers. RegistersQQ%~7 are used as data registers for bit and
bit field (1 to 32 bits), byte (8 b~~)j’’hord (16 bit), long-word (32 bit), and quad-
~:}
.
word (64 bit) operations. ,~~~jsters AO–A6 and the user, interrupt, and master
stack pointers are addreW’~@gfsters that can be used as software stack pointers
,, l,.$,
.,?..,.
the address registers can be used for
registers (DO–D7, AO–A7) can be used
4
MC68020 TECHNICAL
DATA
MOTOROLA
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