a
FEATURES
PERFORMANCE
25 ns Instruction Cycle Time from 20 MHz Crystal
@ 5.0 Volts
40 MIPS Sustained Performance
Single-Cycle Instruction Execution
Single-Cycle Context Switch
3-Bus Architecture Allows Dual Operand Fetches in
Every Instruction Cycle
Multifunction Instructions
Power-Down Mode Featuring Low CMOS Standby
Power Dissipation with 100 Cycle Recovery from
Power-Down Condition
Low Power Dissipation in Idle Mode
INTEGRATION
ADSP-2100 Family Code Compatible, with Instruction
Set Extensions
80K Bytes of On-Chip RAM, Configured as
16K Words On-Chip Program Memory RAM
16K Words On-Chip Data Memory RAM
Dual Purpose Program Memory for Both Instruction
and Data Storage
Independent ALU, Multiplier/Accumulator, and Barrel
Shifter Computational Units
Two Independent Data Address Generators
Powerful Program Sequencer Provides
Zero Overhead Looping
Conditional Instruction Execution
Programmable 16-Bit Interval Timer with Prescaler
128-Lead TQFP/128-Lead PQFP
SYSTEM INTERFACE
16-Bit Internal DMA Port for High Speed Access to
On-Chip Memory
4 MByte Memory Interface for Storage of Data Tables
and Program Overlays
8-Bit DMA to Byte Memory for Transparent
Program and Data Memory Transfers
I/O Memory Interface with 2048 Locations Supports
Parallel Peripherals
Programmable Memory Strobe and Separate I/O Memory
Space Permits “Glueless” System Design
Programmable Wait State Generation
Two Double-Buffered Serial Ports with Companding
Hardware and Automatic Data Buffering
Automatic Booting of On-Chip Program Memory from
Byte-Wide External Memory, e.g., EPROM, or
Through Internal DMA Port
Six External Interrupts
13 Programmable Flag Pins Provide Flexible System
Signaling
ICE-Port™ Emulator Interface Supports Debugging
in Final Systems
ICE-Port is a trademark of Analog Devices, Inc.
DATA ADDRESS
GENERATORS
DAG 1 DAG 2
PROGRAM
SEQUENCER
DSP Microcomputer
ADSP-2181
FUNCTIONAL BLOCK DIAGRAM
POWER-DOWN
CONTROL
MEMORY
PROGRAM
MEMORY
DATA
MEMORY
PROGRAMMABLE
I/O
FLAGS
BYTE DMA
CONTROLLER
EXTERNAL
ADDRESS
BUS
EXTERNAL
DATA BUS
PROGRAM MEMORY ADDRESS
DATA MEMORY ADDRESS
PROGRAM MEMORY DATA
DATA MEMORY DATA
ARITHMETIC UNITS
ALU
MAC
SHIFTER
SERIAL PORTS
SPORT 0
SPORT 1
TIMER
INTERNAL
DMA
PORT
DMA BUS
ADSP-2100 BASE
ARCHITECTURE
GENERAL DESCRIPTION
The ADSP-2181 is a single-chip microcomputer optimized for
digital signal processing (DSP) and other high speed numeric
processing applications.
The ADSP-2181 combines the ADSP-2100 family base archi-
tecture (three computational units, data address generators and
a program sequencer) with two serial ports, a 16-bit internal
DMA port, a byte DMA port, a programmable timer, Flag I/O,
extensive interrupt capabilities, and on-chip program and data
memory.
The ADSP-2181 integrates 80K bytes of on-chip memory con-
figured as 16K words (24-bit) of program RAM, and 16K words
(16-bit) of data RAM. Power-down circuitry is also provided to
meet the low power needs of battery operated portable equip-
ment. The ADSP-2181 is available in 128-lead TQFP and 128-
lead PQFP packages.
In addition, the ADSP-2181 supports new instructions, which
include bit manipulations—bit set, bit clear, bit toggle, bit test—
new ALU constants, new multiplication instruction (x squared),
biased rounding, result free ALU operations, I/O memory trans-
fers and global interrupt masking for increased flexibility.
Fabricated in a high speed, double metal, low power, CMOS
process, the ADSP-2181 operates with a 25 ns instruction cycle
time. Every instruction can execute in a single processor cycle.
The ADSP-2181’s flexible architecture and comprehensive
instruction set allow the processor to perform multiple opera-
tions in parallel. In one processor cycle the ADSP-2181 can:
• Generate the next program address
• Fetch the next instruction
• Perform one or two data moves
• Update one or two data address pointers
• Perform a computational operation
REV. D
Information furnished by Analog Devices is believed to be accurate and
reliable. However, no responsibility is assumed by Analog Devices for its
use, nor for any infringements of patents or other rights of third parties
which may result from its use. No license is granted by implication or
otherwise under any patent or patent rights of Analog Devices.
One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A.
Tel: 781/329-4700
World Wide Web Site: http://www.analog.com
Fax: 781/326-8703
© Analog Devices, Inc., 1998
ADSP-2181
This takes place while the processor continues to:
• Receive and transmit data through the two serial ports
• Receive and/or transmit data through the internal DMA port
• Receive and/or transmit data through the byte DMA port
• Decrement timer
Development System
Additional Information
The ADSP-2100 Family Development Software, a complete
set of tools for software and hardware system development,
supports the ADSP-2181. The System Builder provides a high
level method for defining the architecture of systems under
development. The Assembler has an algebraic syntax that is easy
to program and debug. The Linker combines object files into
an executable file. The Simulator provides an interactive
instruction-level simulation with a reconfigurable user interface
to display different portions of the hardware environment. A
PROM Splitter generates PROM programmer compatible files.
The C Compiler, based on the Free Software Foundation’s
GNU C Compiler, generates ADSP-2181 assembly source
code. The source code debugger allows programs to be cor-
rected in the C environment. The Runtime Library includes over
100 ANSI-standard mathematical and DSP-specific functions.
The EZ-KIT Lite is a hardware/software kit offering a complete
development environment for the entire ADSP-21xx family: an
ADSP-2181 evaluation board with PC monitor software plus
Assembler, Linker, Simulator, and PROM Splitter software.
The ADSP-218x EZ-KIT Lite is a low-cost, easy to use hard-
ware platform on which you can quickly get started with your
DSP software design. The EZ-KIT Lite includes the following
features:
• 33 MHz ADSP-2181
• Full 16-bit Stereo Audio I/O with AD1847 SoundPort
®
Codec
• RS-232 Interface to PC with Windows 3.1 Control Software
• Stand-Alone Operation with Socketed EPROM
• EZ-ICE
®
Connector for Emulator Control
• DSP Demo Programs
The ADSP-218x EZ-ICE Emulator aids in the hardware debug-
ging of ADSP-218x systems. The emulator consists of hard-
ware, host computer resident software and the target board
connector. The ADSP-218x integrates on-chip emulation sup-
port with a 14-pin ICE-Port interface. This interface provides a
simpler target board connection requiring fewer mechanical
clearance considerations than other ADSP-2100 Family EZ-ICEs.
The ADSP-218x device need not be removed from the target
system when using the EZ-ICE, nor are any adapters needed. Due
to the small footprint of the EZ-ICE connector, emulation can be
supported in final board designs.
The EZ-ICE performs a full range of functions, including:
• In-target operation
• Up to 20 breakpoints
• Single-step or full-speed operation
• Registers and memory values can be examined and altered
• PC upload and download functions
• Instruction-level emulation of program booting and execution
• Complete assembly and disassembly of instructions
• C source-level debugging
See the Designing An EZ-ICE-Compatible Target System sec-
tion of this data sheet for exact specifications of the EZ-ICE target
board connector.
EZ-ICE and SoundPort are registered trademarks of Analog Devices, Inc.
This data sheet provides a general overview of ADSP-2181
functionality. For additional information on the architecture and
instruction set of the processor, refer to the
ADSP-2100 Family
User’s Manual, Third Edition.
For more information about the
development tools, refer to the
ADSP-2100 Family Development
Tools Data Sheet.
ARCHITECTURE OVERVIEW
The ADSP-2181 instruction set provides flexible data moves
and multifunction (one or two data moves with a computation)
instructions. Every instruction can be executed in a single pro-
cessor cycle. The ADSP-2181 assembly language uses an alge-
braic syntax for ease of coding and readability. A comprehensive
set of development tools supports program development.
Figure 1 is an overall block diagram of the ADSP-2181. The
processor contains three independent computational units: the
ALU, the multiplier/accumulator (MAC) and the shifter. The
computational units process 16-bit data directly and have provi-
sions to support multiprecision computations. The ALU per-
forms a standard set of arithmetic and logic operations; division
primitives are also supported. The MAC performs single-cycle
multiply, multiply/add and multiply/subtract operations with
40 bits of accumulation. The shifter performs logical and arith-
metic shifts, normalization, denormalization and derive expo-
nent operations. The shifter can be used to efficiently implement
numeric format control including multiword and block floating-
point representations.
The internal result (R) bus connects the computational units so
that the output of any unit may be the input of any unit on the
next cycle.
A powerful program sequencer and two dedicated data address
generators ensure efficient delivery of operands to these computa-
tional units. The sequencer supports conditional jumps, subroutine
calls and returns in a single cycle. With internal loop counters and
loop stacks, the ADSP-2181 executes looped code with zero over-
head; no explicit jump instructions are required to maintain loops.
Two data address generators (DAGs) provide addresses for
simultaneous dual operand fetches (from data memory and
program memory). Each DAG maintains and updates four
address pointers. Whenever the pointer is used to access data
(indirect addressing), it is post-modified by the value of one of
four possible modify registers. A length value may be associated
with each pointer to implement automatic modulo addressing
for circular buffers.
Efficient data transfer is achieved with the use of five internal
buses:
• Program Memory Address (PMA) Bus
• Program Memory Data (PMD) Bus
• Data Memory Address (DMA) Bus
• Data Memory Data (DMD) Bus
• Result (R) Bus
The two address buses (PMA and DMA) share a single external
address bus, allowing memory to be expanded off-chip, and the
two data buses (PMD and DMD) share a single external data
bus. Byte memory space and I/O memory space also share the
external buses.
Program memory can store both instructions and data, permit-
ting the ADSP-2181 to fetch two operands in a single cycle,
one from program memory and one from data memory. The
–2–
REV. D
ADSP-2181
ADSP-2181 can fetch an operand from program memory and
the next instruction in the same cycle.
In addition to the address and data bus for external memory
connection, the ADSP-2181 has a 16-bit Internal DMA port
(IDMA port) for connection to external systems. The IDMA
port is made up of 16 data/address pins and five control pins.
The IDMA port provides transparent, direct access to the DSPs
on-chip program and data RAM.
An interface to low cost byte-wide memory is provided by the
Byte DMA port (BDMA port). The BDMA port is bidirectional
and can directly address up to four megabytes of external RAM
or ROM for off-chip storage of program overlays or data tables.
The byte memory and I/O memory space interface supports slow
memories and I/O memory-mapped peripherals with program-
mable wait state generation. External devices can gain control of
external buses with bus request/grant signals (BR,
BGH
and
BG).
One execution mode (Go Mode) allows the ADSP-2181 to con-
tinue running from on-chip memory. Normal execution mode
requires the processor to halt while buses are granted.
The ADSP-2181 can respond to 13 possible interrupts, eleven
of which are accessible at any given time. There can be up to six
external interrupts (one edge-sensitive, two level-sensitive and
three configurable) and seven internal interrupts generated by
the timer, the serial ports (SPORTs), the Byte DMA port and
the power-down circuitry. There is also a master
RESET
signal.
The two serial ports provide a complete synchronous serial inter-
face with optional companding in hardware and a wide variety of
framed or frameless data transmit and receive modes of operation.
Each port can generate an internal programmable serial clock or
accept an external serial clock.
The ADSP-2181 provides up to 13 general-purpose flag pins.
The data input and output pins on SPORT1 can be alternatively
configured as an input flag and an output flag. In addition, there
are eight flags that are programmable as inputs or outputs and
three flags that are always outputs.
A programmable interval timer generates periodic interrupts. A
16-bit count register (TCOUNT) is decremented every
n
pro-
cessor cycles, where
n
is a scaling value stored in an 8-bit regis-
ter (TSCALE). When the value of the count register reaches
zero, an interrupt is generated and the count register is reloaded
from a 16-bit period register (TPERIOD).
Serial Ports
The ADSP-2181 incorporates two complete synchronous serial
ports (SPORT0 and SPORT1) for serial communications and
multiprocessor communication.
Here is a brief list of the capabilities of the ADSP-2181 SPORTs.
Refer to the
ADSP-2100 Family User’s Manual, Third Edition
for
further details.
• SPORTs are bidirectional and have a separate, double-
buffered transmit and receive section.
• SPORTs can use an external serial clock or generate their
own serial clock internally.
• SPORTs have independent framing for the receive and trans-
mit sections. Sections run in a frameless mode or with frame
synchronization signals internally or externally generated.
Frame sync signals are active high or inverted, with either of
two pulsewidths and timings.
21xx CORE
ADSP-2181 INTEGRATION
POWER-
DOWN
CONTROL
LOGIC
INSTRUCTION
REGISTER
PROGRAM
SRAM
16K 24
DATA
SRAM
16K 16
2
DATA
ADDRESS
GENERATOR
#1
DATA
ADDRESS
GENERATOR
#2
PMA BUS
BYTE
DMA
CONTROLLER
PROGRAMMABLE
I/O
FLAGS
8
3
PROGRAM
SEQUENCER
14
PMA BUS
14
MUX
EXTERNAL
ADDRESS
BUS
DMA BUS
14
DMA BUS
PMD BUS
24
PMD BUS
EXTERNAL
DATA
BUS
DMD
BUS
MUX
24
BUS
EXCHANGE
DMD BUS
16
INPUT REGS
INPUT REGS
INPUT REGS
INPUT REGS
MAC
MAC
INPUT REGS
SHIFTER
COMPANDING
CIRCUITRY
TIMER
TRANSMIT REG
TRANSMIT REG
RECEIVE REG
SERIAL
PORT 0
RECEIVE REG
SERIAL
PORT 0
ALU
ALU
INTERNAL
DMA
PORT
16
OUTPUT REGS
OUTPUT REGS
OUTPUT REGS
OUTPUT REGS
OUTPUT REGS
16
R BUS
4
INTERRUPTS
5
5
Figure 1. ADSP-2181 Block Diagram
REV. D
–3–
ADSP-2181
• SPORTs support serial data word lengths from 3 to 16 bits
and provide optional A-law and
µ-law
companding according
to CCITT recommendation G.711.
• SPORT receive and transmit sections can generate unique
interrupts on completing a data word transfer.
• SPORTs can receive and transmit an entire circular buffer of
data with only one overhead cycle per data word. An interrupt
is generated after a data buffer transfer.
• SPORT0 has a multichannel interface to selectively receive
and transmit a 24- or 32-word, time-division multiplexed,
serial bitstream.
• SPORT1 can be configured to have two external interrupts
(IRQ0 and
IRQ1)
and the Flag In and Flag Out signals. The
internally generated serial clock may still be used in this
configuration.
Pin Descriptions
Pin
Name(s)
#
of
Pins
Input/
Output Function
O
I/O
I/O
I
I
I
I/O
O
I
O
O
I/O
*
*
*
*
*
*
*
*
*
–
–
Processor Clock Output
Serial Port I/O Pins
Serial Port 1
or
Two External
IRQs,
Flag In and Flag Out
IDMA Port Read/Write Inputs
IDMA Port Select
IDMA Port Address Latch
Enable
IDMA Port Address/Data Bus
IDMA Port Access Ready
Acknowledge
Power-Down Control
Power-Down Control
Output Flags
Programmable I/O Pins
(Emulator Only*)
(Emulator Only*)
(Emulator Only*)
(Emulator Only*)
(Emulator Only*)
(Emulator Only*)
(Emulator Only*)
(Emulator Only*)
(Emulator Only*)
Ground Pins
Power Supply Pins
CLKOUT 1
SPORT0
5
SPORT1
5
IRD, IWR
IS
IAL
IAD
IACK
PWD
PWDACK
FL0, FL1,
FL2
PF7:0
EE
EBR
EBG
ERESET
EMS
EINT
ECLK
ELIN
ELOUT
GND
VDD
2
1
1
16
1
1
1
3
8
1
1
1
1
1
1
1
1
1
11
6
The ADSP-2181 is available in 128-lead TQFP and 128-lead
PQFP packages.
PIN FUNCTION DESCRIPTIONS
Pin
Name(s)
Address
Data
#
of
Pins
14
24
Input/
Output Function
O
I/O
Address Output Pins for Program,
Data, Byte, and I/O Spaces
Data I/O Pins for Program and
Data Memory Spaces (8 MSBs
Are Also Used as Byte Space
Addresses)
Processor Reset Input
Edge- or Level-Sensitive
Interrupt Request
Level-Sensitive Interrupt
Requests
Edge-Sensitive Interrupt
Request
Bus Request Input
Bus Grant Output
Bus Grant Hung Output
Program Memory Select Output
Data Memory Select Output
Byte Memory Select Output
I/O Space Memory Select Output
Combined Memory Select Output
Memory Read Enable Output
Memory Write Enable Output
Memory Map Select Input
Boot Option Control Input
Clock or Quartz Crystal Input
RESET
IRQ2
IRQL0,
IRQL1
IRQE
BR
BG
BGH
PMS
DMS
BMS
IOMS
CMS
RD
WR
MMAP
BMODE
CLKIN,
XTAL
1
1
I
I
2
1
1
1
1
1
1
1
1
1
1
1
1
1
2
I
I
I
O
O
O
O
O
O
O
O
O
I
I
I
*These ADSP-2181 pins must be connected
only
to the EZ-ICE connector in
the target system. These pins have no function except during emulation, and
do not require pull-up or pull-down resistors.
Interrupts
The interrupt controller allows the processor to respond to the
eleven possible interrupts and reset with minimum overhead.
The ADSP-2181 provides four dedicated external interrupt
input pins,
IRQ2, IRQL0, IRQL1
and
IRQE.
In addition,
SPORT1 may be reconfigured for
IRQ0, IRQ1,
FLAG_IN and
FLAG_OUT, for a total of six external interrupts. The ADSP-
2181 also supports internal interrupts from the timer, the byte
DMA port, the two serial ports, software and the power-down
control circuit. The interrupt levels are internally prioritized and
individually maskable (except power down and reset). The
IRQ2, IRQ0
and
IRQ1
input pins can be programmed to be
either level- or edge-sensitive.
IRQL0
and
IRQL1
are level-
sensitive and
IRQE
is edge sensitive. The priorities and vector
addresses of all interrupts are shown in Table I.
–4–
REV. D
ADSP-2181
Table I. Interrupt Priority and Interrupt Vector Addresses
Power-Down
Source of Interrupt
Reset (or Power-Up with PUCR = 1)
Power-Down (Nonmaskable)
IRQ2
IRQL1
IRQL0
SPORT0 Transmit
SPORT0 Receive
IRQE
BDMA Interrupt
SPORT1 Transmit or
IRQ1
SPORT1 Receive or
IRQ0
Timer
Interrupt Vector
Address (Hex)
0000 (Highest
Priority)
002C
0004
0008
000C
0010
0014
0018
001C
0020
0024
0028 (Lowest
Priority)
The ADSP-2181 processor has a low power feature that lets
the processor enter a very low power dormant state through
hardware or software control. Here is a brief list of power-
down features. For detailed information about the power-
down feature, refer to the
ADSP-2100 Family User’s Manual,
Third Edition,
“System Interface” chapter.
• Quick recovery from power-down. The processor begins
executing instructions in as few as 100 CLKIN cycles.
• Support for an externally generated TTL or CMOS
processor clock. The external clock can continue running
during power-down without affecting the lowest power
rating and 100 CLKIN cycle recovery.
• Support for crystal operation includes disabling the oscil-
lator to save power (the processor automatically waits 4096
CLKIN cycles for the crystal oscillator to start and stabi-
lize), and letting the oscillator run to allow 100 CLKIN
cycle start up.
• Power-down is initiated by either the power-down pin
(PWD) or the software power-down force bit.
• Interrupt support allows an unlimited number of instruc-
tions to be executed before optionally powering down.
The power-down interrupt also can be used as a non-
maskable, edge-sensitive interrupt.
• Context clear/save control allows the processor to con-
tinue where it left off or start with a clean context when
leaving the power-down state.
• The
RESET
pin also can be used to terminate power-
down.
• Power-down acknowledge pin indicates when the proces-
sor has entered power-down.
Idle
Interrupt routines can either be nested with higher priority
interrupts taking precedence or processed sequentially. Inter-
rupts can be masked or unmasked with the IMASK register.
Individual interrupt requests are logically ANDed with the bits
in IMASK; the highest priority unmasked interrupt is then
selected. The power-down interrupt is nonmaskable.
The ADSP-2181 masks all interrupts for one instruction cycle
following the execution of an instruction that modifies the
IMASK register. This does not affect serial port autobuffering
or DMA transfers.
The interrupt control register, ICNTL, controls interrupt nest-
ing and defines the
IRQ0, IRQ1
and
IRQ2
external interrupts to
be either edge- or level-sensitive. The
IRQE
pin is an external
edge-sensitive interrupt and can be forced and cleared. The
IRQL0
and
IRQL1
pins are external level-sensitive interrupts.
The IFC register is a write-only register used to force and clear
interrupts.
On-chip stacks preserve the processor status and are automati-
cally maintained during interrupt handling. The stacks are twelve
levels deep to allow interrupt, loop and subroutine nesting.
The following instructions allow global enable or disable servic-
ing of the interrupts (including power down), regardless of the
state of IMASK. Disabling the interrupts does not affect serial
port autobuffering or DMA.
ENA INTS;
DIS INTS;
When the processor is reset, interrupt servicing is enabled.
LOW POWER OPERATION
When the ADSP-2181 is in the Idle Mode, the processor
waits indefinitely in a low power state until an interrupt
occurs. When an unmasked interrupt occurs, it is serviced;
execution then continues with the instruction following the
IDLE
instruction.
Slow Idle
The
IDLE
instruction is enhanced on the ADSP-2181 to let
the processor’s internal clock signal be slowed, further
reducing power consumption. The reduced clock fre-
quency, a programmable fraction of the normal clock rate,
is specified by a selectable divisor given in the
IDLE
in-
struction. The format of the instruction is
IDLE (n);
where
n
= 16, 32, 64 or 128. This instruction keeps the
processor fully functional, but operating at the slower clock
rate. While it is in this state, the processor’s other internal
clock signals, such as SCLK, CLKOUT and timer clock,
are reduced by the same ratio. The default form of the
instruction, when no clock divisor is given, is the standard
IDLE
instruction.
The ADSP-2181 has three low power modes that significantly
reduce the power dissipation when the device operates under
standby conditions. These modes are:
• Power-Down
• Idle
• Slow Idle
The CLKOUT pin may also be disabled to reduce external
power dissipation.
REV. D
–5–
NXP MCU
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