CD4000UBK/3 datasheet, PDF - EEWORLD Datasheet

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CD4000UBK/3: DescriptionIC,LOGIC GATE,DUAL 3-INPUT NOR,CMOS,FP,14PIN,CERAMIC; Categorylogic logic; File Size825KB，8 Pages; ManufacturerRenesas Electronics Corporation; Websitehttps://www.renesas.com/

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CD4000UBK/3 Overview

IC,LOGIC GATE,DUAL 3-INPUT NOR,CMOS,FP,14PIN,CERAMIC

CD4000UBK/3 Parametric

Parameter Name	Attribute value
Maker	Renesas Electronics Corporation
package instruction	DFP, FL14,.3
Reach Compliance Code	compliant
JESD-30 code	R-XDFP-F14
Load capacitance (CL)	50 pF
Number of terminals	14
Maximum operating temperature	125 °C
Minimum operating temperature	-55 °C
Package body material	CERAMIC
encapsulated code	DFP
Encapsulate equivalent code	FL14,.3
Package shape	RECTANGULAR
Package form	FLATPACK
power supply	5/15 V
Prop。Delay @ Nom-Sup	120 ns
Certification status	Not Qualified
Schmitt trigger	NO
Filter level	38535Q/M;38534H;883B
surface mount	YES
technology	CMOS
Temperature level	MILITARY
Terminal form	FLAT
Terminal pitch	1.27 mm
Terminal location	DUAL

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Description	IC,LOGIC GATE,DUAL 3-INPUT NOR,CMOS,FP,14PIN,CERAMIC	IC,LOGIC GATE,DUAL 4-INPUT NOR,CMOS,DIP,14PIN,CERAMIC	IC,LOGIC GATE,DUAL 4-INPUT NOR,CMOS,DIP,14PIN,PLASTIC	IC,LOGIC GATE,DUAL 4-INPUT NOR,CMOS,DIP,14PIN,CERAMIC	IC,LOGIC GATE,DUAL 4-INPUT NOR,CMOS,DIE	IC,LOGIC GATE,DUAL 3-INPUT NOR,CMOS,DIP,14PIN,CERAMIC	IC,LOGIC GATE,3 3-INPUT NOR,CMOS,DIP,14PIN,PLASTIC	IC,LOGIC GATE,3 3-INPUT NOR,CMOS,DIE	IC,LOGIC GATE,3 3-INPUT NOR,CMOS,FP,14PIN,CERAMIC
Reach Compliance Code	compliant	not_compliant	not_compliant	not_compliant	compliant	not_compliant	not_compliant	compliant	compliant
Load capacitance (CL)	50 pF	50 pF	50 pF	50 pF	50 pF	50 pF	50 pF	50 pF	50 pF
Maximum operating temperature	125 °C	125 °C	85 °C	125 °C	125 °C	125 °C	85 °C	125 °C	125 °C
Minimum operating temperature	-55 °C	-55 °C	-40 °C	-55 °C	-55 °C	-55 °C	-40 °C	-55 °C	-55 °C
Encapsulate equivalent code	FL14,.3	DIP14,.3	DIP14,.3	DIP14,.3	DIE OR CHIP	DIP14,.3	DIP14,.3	DIE OR CHIP	FL14,.3
power supply	5/15 V	5/15 V	5/15 V	5/15 V	5/15 V	5/15 V	5/15 V	5/15 V	5/15 V
Prop。Delay @ Nom-Sup	120 ns	120 ns	120 ns	120 ns	120 ns	120 ns	120 ns	120 ns	120 ns
Certification status	Not Qualified	Not Qualified	Not Qualified	Not Qualified	Not Qualified	Not Qualified	Not Qualified	Not Qualified	Not Qualified
Schmitt trigger	NO	NO	NO	NO	NO	NO	NO	NO	NO
technology	CMOS	CMOS	CMOS	CMOS	CMOS	CMOS	CMOS	CMOS	CMOS
Temperature level	MILITARY	MILITARY	INDUSTRIAL	MILITARY	MILITARY	MILITARY	INDUSTRIAL	MILITARY	MILITARY
Maker	Renesas Electronics Corporation	-	-	-	-	Renesas Electronics Corporation	Renesas Electronics Corporation	Renesas Electronics Corporation	Renesas Electronics Corporation
package instruction	DFP, FL14,.3	DIP, DIP14,.3	DIP, DIP14,.3	DIP, DIP14,.3	, DIE OR CHIP	-	DIP, DIP14,.3	, DIE OR CHIP	DFP, FL14,.3
JESD-30 code	R-XDFP-F14	R-XDIP-T14	R-PDIP-T14	R-XDIP-T14	-	R-XDIP-T14	R-PDIP-T14	-	R-XDFP-F14
Number of terminals	14	14	14	14	-	14	14	-	14
Package body material	CERAMIC	CERAMIC	PLASTIC/EPOXY	CERAMIC	-	CERAMIC	PLASTIC/EPOXY	-	CERAMIC
encapsulated code	DFP	DIP	DIP	DIP	-	DIP	DIP	-	DFP
Package shape	RECTANGULAR	RECTANGULAR	RECTANGULAR	RECTANGULAR	-	RECTANGULAR	RECTANGULAR	-	RECTANGULAR
Package form	FLATPACK	IN-LINE	IN-LINE	IN-LINE	-	IN-LINE	IN-LINE	-	FLATPACK
surface mount	YES	NO	NO	NO	-	NO	NO	-	YES
Terminal form	FLAT	THROUGH-HOLE	THROUGH-HOLE	THROUGH-HOLE	-	THROUGH-HOLE	THROUGH-HOLE	-	FLAT
Terminal pitch	1.27 mm	2.54 mm	2.54 mm	2.54 mm	-	2.54 mm	2.54 mm	-	1.27 mm
Terminal location	DUAL	DUAL	DUAL	DUAL	-	DUAL	DUAL	-	DUAL
Is it Rohs certified?	-	incompatible	incompatible	incompatible	-	incompatible	incompatible	-	-
JESD-609 code	-	e0	e0	e0	-	e0	e0	-	-
Logic integrated circuit type	-	NOR GATE	NOR GATE	NOR GATE	NOR GATE	-	NOR GATE	NOR GATE	NOR GATE
Terminal surface	-	Tin/Lead (Sn/Pb)	Tin/Lead (Sn/Pb)	Tin/Lead (Sn/Pb)	-	Tin/Lead (Sn/Pb)	Tin/Lead (Sn/Pb)	-	-

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