B32621A6153K189 datasheet, PDF

B32621A6153K189: DescriptionCAPACITOR, METALLIZED FILM, POLYPROPYLENE, 630V, 0.015uF, THROUGH HOLE MOUNT, RADIAL LEADED; CategoryPassive components capacitor; File Size613KB，19 Pages; ManufacturerEPCOS (TDK); Environmental Compliance

Download Datasheet Parametric View All

B32621A6153K189 Overview

CAPACITOR, METALLIZED FILM, POLYPROPYLENE, 630V, 0.015uF, THROUGH HOLE MOUNT, RADIAL LEADED

Parameter Name	Attribute value
Is it lead-free?	Lead free
Is it Rohs certified?	conform to
Maker	EPCOS (TDK)
package instruction	, 5120
Reach Compliance Code	compliant
ECCN code	EAR99
Other features	RATED AC VOLTAGE (V): 400
capacitance	0.015 µF
Capacitor type	FILM CAPACITOR
dielectric materials	POLYPROPYLENE
high	11 mm
JESD-609 code	e3
length	13 mm
Installation features	THROUGH HOLE MOUNT
negative tolerance	10%
Number of terminals	2
Maximum operating temperature	85 °C
Minimum operating temperature	-55 °C
Package shape	RECTANGULAR PACKAGE
Package form	Radial
method of packing	TR
positive tolerance	10%
Rated (AC) voltage (URac)	400 V
Rated (DC) voltage (URdc)	630 V
size code	5120
surface mount	NO
Terminal surface	Matte Tin (Sn)
Terminal pitch	10 mm
Terminal shape	WIRE
width	5 mm

Film Capacitors

Metallized Polypropylene Film Capacitors (MKP)

Series/Type:

Date:

B32620 ... B32621

August 2004

information contained therein without EPCOS' prior express consent is prohibited.

Purchase orders are subject to the General Conditions for the Supply of Products and Services of the Electrical

and Electronics Industry recommended by the ZVEI (German Electrical and Electronic Manufacturers' Associ-

ation), unless otherwise agreed.

[Design Tools] Virtex-5 LX110T Newbie Quick Start EDK Experiment: The software for this experiment is ISE12.2, and the hardware is Virtex-5 LX110T....; GONGHCU FPGA/CPLD

debug: I am responsible for a product of the company recently. I have completed the schematic diagram, layout and debugging by myself. But now I have encountered a bottleneck in debugging. The voltage is nor...; 樱花锦 PCB Design

The USB2.0 port of GL3520 USB3.0 HUB cannot be recognized: [i=s]This post was last edited by LuJianchang on 2020-12-18 15:28[/i]Regarding the GL3520 USB3.0 HUB, the USB2.0 interface cannot recognize the USB device due to plugging and unplugging the USB3.0 int...; LuJianchang PCB Design

Do you know how a Verilog HDL program is structured?: ...; 至芯科技FPGA大牛 FPGA/CPLD

The problem of finding the difference of the system timer, please help me: CTimeSpan span = SysStopTime - SysStartTime; where SysStopTime and SysStartTime are of CString type, I want to calculate the difference and then display it, for example, output the difference through ...; ccqingzhi Embedded System

I would like to ask about the redrawing problem of the cedit control. The c++ side has also been posted~: When running application software on Windows CE, the CEdit control refreshes slowly when there are many interfaces. Is there a way to handle these controls like copying pictures? How to solve the prob...; xingtao Embedded System

Shortcut: S0 S1 S2 S3 S4 S5 S6 S7 S8 S9 SA SB SC SD SE SF SG SH SI SJ SK SL SM SN SO SP SQ SR SS ST SU SV SW SX SY SZ T0 T1 T2 T3 T4 T5 T6 T7 T8 T9 TA TB TC TD TE TF TG TH TI TJ TK TL TM TN TO TP TQ TR TS TT TU TV TW TX TY TZ U0 U1 U2 U3 U4 U6 U7 U8 UA UB UC UD UE UF UG UH UI UJ UK UL UM UN UP UQ UR US UT UU UV UW UX UZ V0 V1 V2 V3 V4 V5 V6 V7 V8 V9 VA VB VC VD VE VF VG VH VI VJ VK VL VM VN VO VP VQ VR VS VT VU VV VW VX VY VZ W0 W1 W2 W3 W4 W5 W6 W7 W8 W9 WA WB WC WD WE WF WG WH WI WJ WK WL WM WN WO WP WR WS WT WU WV WW WY X0 X1 X2 X3 X4 X5 X7 X8 X9 XA XB XC XD XE XF XG XH XK XL XM XN XO XP XQ XR XS XT XU XV XW XX XY XZ Y0 Y1 Y2 Y4 Y5 Y6 Y9 YA YB YC YD YE YF YG YH YK YL YM YN YP YQ YR YS YT YX Z0 Z1 Z2 Z3 Z4 Z5 Z6 Z8 ZA ZB ZC ZD ZE ZF ZG ZH ZJ ZL ZM ZN ZP ZR ZS ZT ZU ZV ZW ZX ZY

Popular Components