STEL-2050A
Data Sheet
STEL-2050A
Convolutional Encoder
Viterbi Decoder
R
FEATURES
s
Constraint Length 7
s
Rates
1
/
3
,
1
/
2
,
2
/
3
* and
3
/
4
* (*Punctured)
s
Built in BER Monitor
s
Programmable Scrambler:
V.35 (CCITT or IESS) or "Invert G2"
s
Coding Gain of 5.2 dB (@ 10
-5
BER, Rate
1
/
2
)
s
Industry Standard Polynomials
G1=171
8
, G2=133
8
, G3=145
8
,
s
All control and data I/O via Microprocessor
Interface
s
Differential Encoder and Decoder
s
Three Bit Soft Decision Inputs in Signed
Magnitude or 2's Complement Formats
s
Low Power Consumption
s
28-pin PLCC and CLDCC Packages
s
Commercial and Military Temperature
Ranges Available
s
Up to 256 Kbps Data Rate (–40° to 85° C)
s
0.6 Micron CMOS Technology
BLOCK DIAGRAM
DIFFERENTIAL
ENCODER
AND V.35
ACLK
SCRAMBLERS DAT
DAT
AIN
CONVOLUTIONAL
ENCODER
"INV G2"
SCRAMBLER
RESET
(TO ALL
REGISTERS)
ENCODER SECTION
SCRAM1-0
2
G3OUT
INT
READ, WRSTB, CSEL
ADDR
DATA
3
4
8
MICROPROCESSOR
INTERFACE,
MODE SELECT
AND CONTROL
G2OUT
G1OUT
3
3
OCLK
ICLK
SYNC
1-0
SM2C
G1D
2-0
G2D
2-0
G3D
2-0
BERR
G1ERR
G2ERR
G3ERR
DOUT
3
2
DRDY
ADDRESS
SEQUENCER
AND
CONTROL LOGIC
DRATE
DECODER SECTION
TRELLIS
RAM
STATE-METRIC
RAM
ADDR
DO DI
DATA
BRANCH METRIC
AND
ADD-COMPARE-
SELECT LOGIC
BER
MONITOR
"INV G2"
DESCRAMBLER
BUFFER
REGISTER
& MUX
PNCG1
PNCG2
MIS
THRESH
3
PATH HISTORY AND
AUTO NODE-SYNC
LOGIC
DIFFERENTIAL
DECODER
AND V.35
DESCRAM-
BLERS
SYNC
SST0
SST1
STEL-2050A
2
FUNCTIONAL DESCRIPTION
Convolutional Encoding and Viterbi Decoding are
used to provide forward error correction (FEC) which
improves digital communication performance over a
noisy link. In satellite communication systems where
transmitter power is limited, FEC techniques can
reduce the required transmission power. The
STEL-2050A is a specialized product designed to
perform this specific communications related
function.
The encoder creates a stream of symbols which are
transmitted at 2 (rate
1
/
2
) or 3 (rate
1
/
3
) times the
information rate. This encoding introduces a high
degree of redundancy which enables accurate
decoding of information despite a high symbol error
rate resulting from a noisy link. The coding overhead
can be reduced at the expense of the coding gain by
puncturing (deleting) some of the symbols. The
STEL-2050A is designed to operate in this way at rates
2
/
3
and
3
/
4
, when 3 symbols are transmitted for every
2 bits encoded (rate
2
/
3
) or 4 symbols are transmitted
for every 3 bits encoded (rate
3
/
4
). The resulting
bandwidth overhead is just 50% and 33% respectively,
compared with 100% at rate
1
/
2
.
The STEL-2050A incorporates all the memories
required to perform these functions. In addition, the
STEL-2050A incorporates a differential encoder and
decoder, three different scrambling algorithms, a BER
monitor and a microprocessor interface. The STEL-
2050A is available in a 28-pin PLCC (plastic leaded
chip carrier) and also in a ceramic leaded chip carrier
(J-bend leads).
PIN CONFIGURATION
2 2 2
4 3 2 1 8 7 6
5
6
7
8
9
10
11
25
24
23
22
21
20
19
Package: 28 pin PLCC (J-bend)
Thermal coefficient,
θ
ja
= 45°/W
0.492"
±.01"
0.175"
max.
Top View
0.020"
min.
0.05" (1)
1 1 1 1 1 1 1
2 3 4 5 6 7 8
0.018"
±.003" (2)
0.450
±.01"
Notes: 1 Tolerance not cumulative
2 Dimension at seating plane
PIN CONNECTIONS
1 V
SS
2 READ
3 CSEL
4 V
DD
5 RESET
6 V
SS
7 ICLK
8
9
10
11
12
13
14
V
SS
OCLK
V
DD
ADDR
3
ADDR
2
ADDR
1
ADDR
0
15
16
17
18
19
20
21
V
SS
DATA
7
DATA
6
V
DD
DATA
5
DATA
4
DATA
3
22
23
24
25
26
27
28
V
SS
DATA
2
DATA
1
DATA
0
INT
I.C.
WRSTB
Notes: 1. I.C. denotes Internal Connection. ThIs pin must be left unconnected. Do not use for a via.
2. Connect all unused inputs to V
SS
, leave unused outputs unconnected.
3
STEL-2050A
FUNCTION BLOCK DESCRIPTION
The convolutional coder is functionally independent
of the decoder. Writing a new data bit into address 4
H
automatically clocks the data down the 7-bit shift
register. The symbols G1, G2, and G3 are generated
from the modulo-2 sum (exclusive-OR) of the inputs to
the 3 generators from the taps on the shift register. The
3 polynomials are 171
8
(G1), 133
8
(G2), and 145
8
(G3).
The three symbols generated for each input data bit are
written into the read mode register at address 5
H
.
At the decoder symbols are written into addresses 0
H
and (for rate
1
/
3
operation only) 1
H
. The
DRATE
bit in
address 2
H
determines whether the decoder operates
in rate
1
/
2
or rate
1
/
3
mode. When operating at rate
1
/
2
the decoding process starts automatically as soon
as data is written into address 0
H
and the G3 data is
ignored by the decoder. When operating at rate
1
/
3
the
G1 and G2 symbols must be written first, since the
decoding process starts automatically as soon as data
is written into address 1
H
. At least 70 cycles of
ICLK
must elapse between each write operation to address
0
H
. (rate
1
/
2
) or 1
H
(rate
1
/
3
) to allow the decoder to
process each data bit.
For hard decision binary symbols the symbol should
be written into bits
G1D2, G2D2
and
G3D2
respectively, and the other symbol bits set high. Three-
bit soft decision symbols may be input in Signed
Magnitude or Two’s Complement code, according to
the setting of the code control bit,
SM2C,
in address 2
H
.
The bit should be set high when using hard decision
data.
A single decoded data bit,
DOUT,
is written into
address 3
H
(read mode) for every set of input symbols.
The data bit corresponding to a particular symbol set
will be output after a delay of 71 symbol sets.
Therefore, when using the STEL-2050A to decode
blocks of data 71 additional dummy zero symbols (G1
and G2 for rate
1
/
3
or G3 for rate
1
/
3
) must be written
into address 0
H
or 1
H
to flush the last 71 decoded data
bits out of the decoder.
Node synchronization (correctly grouping incoming
symbols into G1, G2, and G3 sets) is inherent with
many communication techniques such as TDMA and
spread spectrum systems. If node synchronization is
not an inherent property of the communications link
then the internal auto node sync circuit can be used to
do this. This is accomplished by internally connecting
the node sync outputs (SST0 and
SST1)
to the node
sync inputs (SYNC0 and
SYNC1)
by setting the
AUTONS
bit in address 3
H
high. The threshold for
determining the out of sync condition is user selectable
by means of the
THRESH
2-0
bits in address 2
H
.
A Bit Error Rate Monitor function is provided by re-
encoding the decoded data bits and comparing the
result with a delayed version of the input symbols. The
error information is available in two ways. First, each
time an error occurs the error bits in address 3
H
(read
mode) are set high according to which symbol is found
to be in error, and second a running count of the errors
in a block of data is generated. The length of the block
is determined by the 24-bit word
BPER
23-0
stored in
addresses 6
H
-8
H
multiplied by 1000, i.e.
Block length = 1000 x
BPER
23-0
The number of errors in this period is divided by 8 and
accumulated. If the accumulator overflows during
this period its output will be caused to saturate at a
value of FFFF
H
. At the end of the period the error
divider (÷8) and the error and period accumulators are
cleared and the error count is stored in addresses 7
H
and 8
H
(read mode) so that the actual Bit Error Rate
over this period is:
BER =
8 x
BERCT
15-0
1000 x
BPER
23-0
Note that the BER monitor will indicate an error each
time an input symbol is punctured, so that the BER
indicated by the
BERCT
15-0
output will not be valid
when using punctured codes. In addition, the error
divider truncates the error count since it takes 8 errors
to increase the count by one, and this truncation can
cause significant under-reporting of the error rate
unless the value of
BERCT
15-0
is large enough to make
the truncation insignificantly small.
Further information on the theory of operation of
Viterbi decoders may be obtained from text books such
as "Error-Correcting Codes", by Peterson and Weldon
(MIT Press), or "Error Control Coding", by Lin and
Costello (Prentice-Hall), or papers such as
"Convolutional Codes and their Performance in
Communication Systems", by Dr. A. J. Viterbi, IEEE
Trans. on Communications, October 1971.
INPUT SIGNALS
RESET
Asynchronous master
Reset.
A logic low on this pin
will clear all registers on the STEL-2050AA in both the
encoder and decoder sections of the chip.
RESET
should remain low for at least 3 cycles of
ICLK
to clear
the decoder. A software reset is also effected by
writing dummy data to address 5
H
. The address lines,
WRITE
and
CSEL
lines should generate a valid write
state for at least 3 cycles of
ICLK
to clear the decoder.
ICLK, OCLK
System Clock. A crystal may be connected between
ICLK
and
OCLK
or a CMOS level clock may be fed
into
ICLK.
The clock frequency should be at least 70
times the decoded data rate but no more than 18 MHz.
STEL-2050A
4
MICROPROCESSOR INTERFACE
DATA7-0
All I/O and control functions are accessed via the
DATA
7-0
bus with the associated control signals. The
STEL-2050AA is used as a memory or I/O mapped
peripheral to the host processor.
ADDR3-0
The 4-bit address bus is used to access the various I/O
functions, as shown in the table below. Note that some
addresses contain both read and write registers, i.e.,
the read and write mode registers at these addresses
are separate and contain different data.
WRITE
The
Write
input is used to write data to the
microprocessor data bus. It is active low and is
normally connected to the write line of the host
processor.
READ
The
Read
input is used to read data from the
microprocessor data bus. It is active low and is
normally connected to the read line of the host
processor.
CSEL
The
Chip Select
input can be used to selectively enable
the microprocessor data bus. It is active low.
INT
The
Interrupt
output indicates when the Period
Counter in the BER Monitor has completed a count
period and that a new value of
BERCT
is ready to be
read from addresses 7
H
and 8
H
, when
INT
will go high
for one symbol period.
PNCG1, PNCG2
The
PNCG1
and
PNCG2
bits are used to control the
STEL-2050AA when operating in punctured mode
and are written along with the symbol data. In
unpunctured operation (rates
1
/
2
and
1
/
3
) these bits
should be set low. In punctured operation the
PNCG1
bit must be set high to indicate that the G1 symbol is
punctured and the
PNCG2
bit must be set high to
indicate that the G2 symbol is punctured. A symbol
will be punctured when the
PNCG1
or
PNCG2
bits are
high when
the symbol data is written into address 0
H
.
Zero value metrics will be substituted internally for
the actual metrics corresponding to the
G1
2-0
or
G2
2-0
data at that time.
ADDRESS 2
H
THRESH
2-0
A counter is used to determine the number of either
traceback mismatches or metric renormalizations per
256 bits in the auto node-sync circuit, and the threshold
at which the counter triggers the
SST0
and
SST1
bits
to change states is set with the data on the
THRESH
2-0
bits. The threshold values will be as
shown in the following table.
THRESH
2-0
0
1
2
3
4
5
6
7
Threshold value
1
2
4
8
16
32
64
128
INPUT (WRITE) FUNCTIONS
ADDRESSES 0
H
, 1
H
G1D2-0, G2D2-0, G3D2-0
The three 3-bit soft decision symbols are written into
the registers at addresses 0
H
and 1
H
and the decoding
process begins when the data has been written. When
operating at rate
1
/
2
the operation will begin as soon as
the
G1D
2-0
and
G2D
2-0
data is written into address 0
H
;
when operating at rate
1
/
3
the operation begins when
the
G3D
2-0
data is written into address 1
H
, so that it is
necessary to write the
G1D
2-0
and
G2D
2-0
data first.
The order in which the symbols are entered into the
decoder from the registers depends on the state of the
SYNC0
and
SYNC1
bits. The decoder can make use of
soft decision information, which includes both
polarity information and a confidence measure, to
improve the decoder performance. If hard decision
(single bit) symbols are used the signals are written
into bits
G1D
2
,
G2D
2
and
G3D
2
and the other bits are
set high. See
SM2C
for a description of the input data
codes.
Since the actual error rate obtained will depend on the
signal to noise ratio (E
b
/N
o
) in the signal, the optimum
value of the threshold will also depend on E
b
/N
o
and
should be set accordingly. The actual mismatch or
renomalization count is stored in the read mode
register at address 6
H
.
MIS
Two algorithms for auto node-sync are incorporated
into the STEL-2050AA. When the
MIS
bit is set high
the Traceback
Mismatch
algorithm is selected, and
when this bit is set low the Metric Renormalization
algorithm is selected.
SCRAM0, SCRAM1
The
Scramble
bits are used to enable the three different
scrambler functions included in the STEL-2050AA, as
shown in the following table:
5
STEL-2050A
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