PPC7457RX1000LB datasheet, PDF

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PPC7457RX1000LB: DescriptionRISC Microprocessor, 32-Bit, 1000MHz, CMOS, CBGA483, 29 X 29 MM, 1.27 MM PITCH, CERAMIC, BGA-483; CategoryThe embedded processor and controller Microcontrollers and processors; File Size2MB，87 Pages; ManufacturerMotorola ( NXP ); Websitehttps://www.nxp.com

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PPC7457RX1000LB Overview

RISC Microprocessor, 32-Bit, 1000MHz, CMOS, CBGA483, 29 X 29 MM, 1.27 MM PITCH, CERAMIC, BGA-483

PPC7457RX1000LB Parametric

Parameter Name	Attribute value
Maker	Motorola ( NXP )
package instruction	29 X 29 MM, 1.27 MM PITCH, CERAMIC, BGA-483
Reach Compliance Code	unknown
ECCN code	3A001.A.3
Address bus width	36
bit size	32
boundary scan	YES
maximum clock frequency	167 MHz
External data bus width	64
Format	FLOATING POINT
Integrated cache	YES
JESD-30 code	S-CBGA-B483
length	29 mm
low power mode	YES
Number of terminals	483
Package body material	CERAMIC, METAL-SEALED COFIRED
encapsulated code	BGA
Package shape	SQUARE
Package form	GRID ARRAY
Certification status	Not Qualified
Maximum seat height	3.2 mm
speed	1000 MHz
Maximum supply voltage	1.35 V
Minimum supply voltage	1.25 V
Nominal supply voltage	1.3 V
surface mount	YES
technology	CMOS
Terminal form	BALL
Terminal pitch	1.27 mm
Terminal location	BOTTOM
width	29 mm
uPs/uCs/peripheral integrated circuit type	MICROPROCESSOR, RISC

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Advance Information

MPC7457EC

Rev. 4, 11/2003

MPC7457

RISC Microprocessor

Hardware Specifications

This hardware specification is primarily concerned with the PowerPC™ MPC7457; however,

unless otherwise noted, all information here also applies to the MPC7447. The MPC7457 and

MPC7447 are implementations of the PowerPC microprocessor family of reduced instruction

set computer (RISC) microprocessors. This hardware specification describes pertinent

electrical and physical characteristics of the MPC7457. For functional characteristics of the

processor, refer to the

MPC7450 RISC Microprocessor Family User’s Manual.

This hardware specification contains the following topics:

Topic

Page

Section 1.1, “Overview”

Section 1.2, “Features”

Section 1.3, “Comparison with the MPC7455, MPC7445, MPC7450, MPC7451,

and MPC7441”

Section 1.4, “General Parameters”

Section 1.5, “Electrical and Thermal Characteristics”

Section 1.6, “Pin Assignments”

Section 1.7, “Pinout Listings”

Section 1.8, “Package Description”

Section 1.9, “System Design Information”

Section 1.10, “Document Revision History”

Section 1.11, “Ordering Information”

To locate any published updates for this hardware specification, refer to the website at

http://www.motorola.com/semiconductors.

1.1 Overview

The MPC7457 is the fourth implementation of the fourth generation (G4) microprocessors

from Motorola. The MPC7457 implements the full PowerPC 32-bit architecture and is

targeted at networking and computing systems applications. The MPC7457 consists of a

processor core, a 512-Kbyte L2, and an internal L3 tag and controller that support a glueless

backside L3 cache through a dedicated high-bandwidth interface. The MPC7447 is identical

to the MPC7457 except that it does not support the L3 cache interface.

Features

Figure 1 shows a block diagram of the MPC7457. The core is a high-performance superscalar design

supporting a double-precision floating-point unit and a SIMD multimedia unit. The memory storage

subsystem supports the MPX bus protocol and a subset of the 60x bus protocol to main memory and other

system resources. The L3 interface supports 1, 2, or 4 Mbytes of external SRAM for L3 cache and/or private

memory data. For systems implementing 4 Mbytes of SRAM, a maximum of 2 Mbytes may be used as

cache; the remaining 2 Mbytes must be private memory.

Note that the MPC7457 is a footprint-compatible, drop-in replacement in a MPC7455 application if the core

power supply is 1.3 V.

1.2

Features

This section summarizes features of the MPC7457 implementation of the PowerPC architecture.

Major features of the MPC7457 are as follows:

•

High-performance, superscalar microprocessor

— As many as four instructions can be fetched from the instruction cache at a time.

— As many as three instructions can be dispatched to the issue queues at a time.

— As many as 12 instructions can be in the instruction queue (IQ).

— As many as 16 instructions can be at some stage of execution simultaneously.

— Single-cycle execution for most instructions

— One instruction per clock cycle throughput for most instructions

— Seven-stage pipeline control

Eleven independent execution units and three register files

— Branch processing unit (BPU) features static and dynamic branch prediction

– 128-entry (32-set, four-way set-associative) branch target instruction cache (BTIC), a cache

of branch instructions that have been encountered in branch/loop code sequences. If a target

instruction is in the BTIC, it is fetched into the instruction queue a cycle sooner than it can

be made available from the instruction cache. Typically, a fetch that hits the BTIC provides

the first four instructions in the target stream.

– 2048-entry branch history (BHT) with two bits per entry for four levels of

prediction—not-taken, strongly not-taken, taken, and strongly taken

– Up to three outstanding speculative branches

– Branch instructions that do not update the count register (CTR) or link register (LR) are

often removed from the instruction stream.

– Eight-entry link register stack to predict the target address of Branch Conditional to Link

— Four integer units (IUs) that share 32 GPRs for integer operands

– Three identical IUs (IU1a, IU1b, and IU1c) can execute all integer instructions except

multiply, divide, and move to/from special-purpose register instructions

– IU2 executes miscellaneous instructions including the CR logical operations, integer

multiplication and division instructions, and move to/from special-purpose register

instructions

•

MPC7457 RISC Microprocessor Hardware Specifications

MOTOROLA

Features

•

— Five-stage FPU and a 32-entry FPR file

– Fully IEEE 754-1985-compliant FPU for both single- and double-precision operations

– Supports non-IEEE mode for time-critical operations

– Hardware support for denormalized numbers

– Thirty-two 64-bit FPRs for single- or double-precision operands

— Four vector units and 32-entry vector register file (VRs)

– Vector permute unit (VPU)

– Vector integer unit 1 (VIU1) handles short-latency AltiVec™ integer instructions, such as

vector add instructions (for example,

vaddsbs, vaddshs,

and

vaddsws)

– Vector integer unit 2 (VIU2) handles longer-latency AltiVec integer instructions, such as

vector multiply add instructions (for example,

vmhaddshs, vmhraddshs,

and

vmladduhm)

– Vector floating-point unit (VFPU)

— Three-stage load/store unit (LSU)

– Supports integer, floating-point, and vector instruction load/store traffic

– Four-entry vector touch queue (VTQ) supports all four architected AltiVec data stream

operations

– Three-cycle GPR and AltiVec load latency (byte, half-word, word, vector) with one-cycle

throughput

– Four-cycle FPR load latency (single, double) with one-cycle throughput

– No additional delay for misaligned access within double-word boundary

– Dedicated adder calculates effective addresses (EAs)

– Supports store gathering

– Performs alignment, normalization, and precision conversion for floating-point data

– Executes cache control and TLB instructions

– Performs alignment, zero padding, and sign extension for integer data

– Supports hits under misses (multiple outstanding misses)

– Supports both big- and little-endian modes, including misaligned little-endian accesses

Three issue queues FIQ, VIQ, and GIQ can accept as many as one, two, and three instructions,

respectively, in a cycle. Instruction dispatch requires the following:

— Instructions can be dispatched only from the three lowest IQ entries—IQ0, IQ1, and IQ2

— A maximum of three instructions can be dispatched to the issue queues per clock cycle

— Space must be available in the CQ for an instruction to dispatch (this includes instructions that

are assigned a space in the CQ but not in an issue queue)

Rename buffers

— 16 GPR rename buffers

— 16 FPR rename buffers

— 16 VR rename buffers

Dispatch unit

— Decode/dispatch stage fully decodes each instruction

MPC7457 RISC Microprocessor Hardware Specifications

MOTOROLA

PPC7457RX1000LB Related Products

	PPC7457RX1000LB	MC7447RX1000NB	MC7447RX1000NBR2	PPC7457RX867LB	PPC7457RX1267LB	PPC7447RX1000LB	PPC7447RX867LB	PPC7447RX1200LB	PPC7447RX1267LB	PPC7457RX1200LB
Description	RISC Microprocessor, 32-Bit, 1000MHz, CMOS, CBGA483, 29 X 29 MM, 1.27 MM PITCH, CERAMIC, BGA-483	32-BIT, 1000MHz, RISC PROCESSOR, CBGA360, 25 X 25 MM, 3.20 MM HEIGHT, 1.27 MM PITCH, CERAMIC, FLIP CHIP, BGA-360	32-BIT, 1000MHz, RISC PROCESSOR, CBGA360, 25 X 25 MM, 3.20 MM HEIGHT, 1.27 MM PITCH, CERAMIC, FLIP CHIP, BGA-360	RISC Microprocessor, 32-Bit, 867MHz, CMOS, CBGA483, 29 X 29 MM, 1.27 MM PITCH, CERAMIC, BGA-483	RISC Microprocessor, 32-Bit, 1267MHz, CMOS, CBGA483, 29 X 29 MM, 1.27 MM PITCH, CERAMIC, BGA-483	RISC Microprocessor, 32-Bit, 1000MHz, CMOS, CBGA360, 25 X 25 MM, 1.27 MM PITCH, CERAMIC, BGA-360	RISC Microprocessor, 32-Bit, 867MHz, CMOS, CBGA360, 25 X 25 MM, 1.27 MM PITCH, CERAMIC, BGA-360	RISC Microprocessor, 32-Bit, 1200MHz, CMOS, CBGA360, 25 X 25 MM, 1.27 MM PITCH, CERAMIC, BGA-360	32-BIT, 1267MHz, RISC PROCESSOR, CBGA360, 25 X 25 MM, 1.27 MM PITCH, CERAMIC, BGA-360	RISC Microprocessor, 32-Bit, 1200MHz, CMOS, CBGA483, 29 X 29 MM, 1.27 MM PITCH, CERAMIC, BGA-483
package instruction	29 X 29 MM, 1.27 MM PITCH, CERAMIC, BGA-483	BGA, BGA360,19X19,50	BGA,	29 X 29 MM, 1.27 MM PITCH, CERAMIC, BGA-483	29 X 29 MM, 1.27 MM PITCH, CERAMIC, BGA-483	BGA,	BGA,	BGA,	BGA,	29 X 29 MM, 1.27 MM PITCH, CERAMIC, BGA-483
Reach Compliance Code	unknown	unknown	unknown	unknown	unknown	unknown	unknown	unknown	unknown	unknow
ECCN code	3A001.A.3	3A001.A.3	3A001.A.3	3A001.A.3	3A001.A.3	3A001.A.3	3A001.A.3	3A001.A.3	3A001.A.3	3A001.A.3
Address bus width	36	36	36	36	36	36	36	36	36	36
bit size	32	32	32	32	32	32	32	32	32	32
boundary scan	YES	YES	YES	YES	YES	YES	YES	YES	YES	YES
maximum clock frequency	167 MHz	167 MHz	167 MHz	167 MHz	167 MHz	167 MHz	167 MHz	167 MHz	167 MHz	167 MHz
External data bus width	64	64	64	64	64	64	64	64	64	64
Format	FLOATING POINT	FLOATING POINT	FLOATING POINT	FLOATING POINT	FLOATING POINT	FLOATING POINT	FLOATING POINT	FLOATING POINT	FLOATING POINT	FLOATING POINT
Integrated cache	YES	YES	YES	YES	YES	YES	YES	YES	YES	YES
JESD-30 code	S-CBGA-B483	S-CBGA-B360	S-CBGA-B360	S-CBGA-B483	S-CBGA-B483	S-CBGA-B360	S-CBGA-B360	S-CBGA-B360	S-CBGA-B360	S-CBGA-B483
length	29 mm	25 mm	25 mm	29 mm	29 mm	25 mm	25 mm	25 mm	25 mm	29 mm
low power mode	YES	YES	YES	YES	YES	YES	YES	YES	YES	YES
Number of terminals	483	360	360	483	483	360	360	360	360	483
Package body material	CERAMIC, METAL-SEALED COFIRED	CERAMIC, METAL-SEALED COFIRED	CERAMIC, METAL-SEALED COFIRED	CERAMIC, METAL-SEALED COFIRED	CERAMIC, METAL-SEALED COFIRED	CERAMIC, METAL-SEALED COFIRED	CERAMIC, METAL-SEALED COFIRED	CERAMIC, METAL-SEALED COFIRED	CERAMIC, METAL-SEALED COFIRED	CERAMIC, METAL-SEALED COFIRED
encapsulated code	BGA	BGA	BGA	BGA	BGA	BGA	BGA	BGA	BGA	BGA
Package shape	SQUARE	SQUARE	SQUARE	SQUARE	SQUARE	SQUARE	SQUARE	SQUARE	SQUARE	SQUARE
Package form	GRID ARRAY	GRID ARRAY	GRID ARRAY	GRID ARRAY	GRID ARRAY	GRID ARRAY	GRID ARRAY	GRID ARRAY	GRID ARRAY	GRID ARRAY
Certification status	Not Qualified	Not Qualified	Not Qualified	Not Qualified	Not Qualified	Not Qualified	Not Qualified	Not Qualified	Not Qualified	Not Qualified
Maximum seat height	3.2 mm	3.2 mm	3.2 mm	3.2 mm	3.2 mm	3.2 mm	3.2 mm	3.2 mm	3.2 mm	3.2 mm
speed	1000 MHz	1000 MHz	1000 MHz	867 MHz	1267 MHz	1000 MHz	867 MHz	1200 MHz	1267 MHz	1200 MHz
Maximum supply voltage	1.35 V	1.15 V	1.15 V	1.35 V	1.35 V	1.35 V	1.35 V	1.35 V	1.35 V	1.35 V
Minimum supply voltage	1.25 V	1.05 V	1.05 V	1.25 V	1.25 V	1.25 V	1.25 V	1.25 V	1.25 V	1.25 V
Nominal supply voltage	1.3 V	1.1 V	1.1 V	1.3 V	1.3 V	1.3 V	1.3 V	1.3 V	1.3 V	1.3 V
surface mount	YES	YES	YES	YES	YES	YES	YES	YES	YES	YES
technology	CMOS	CMOS	CMOS	CMOS	CMOS	CMOS	CMOS	CMOS	CMOS	CMOS
Terminal form	BALL	BALL	BALL	BALL	BALL	BALL	BALL	BALL	BALL	BALL
Terminal pitch	1.27 mm	1.27 mm	1.27 mm	1.27 mm	1.27 mm	1.27 mm	1.27 mm	1.27 mm	1.27 mm	1.27 mm
Terminal location	BOTTOM	BOTTOM	BOTTOM	BOTTOM	BOTTOM	BOTTOM	BOTTOM	BOTTOM	BOTTOM	BOTTOM
width	29 mm	25 mm	25 mm	29 mm	29 mm	25 mm	25 mm	25 mm	25 mm	29 mm
uPs/uCs/peripheral integrated circuit type	MICROPROCESSOR, RISC	MICROPROCESSOR, RISC	MICROPROCESSOR, RISC	MICROPROCESSOR, RISC	MICROPROCESSOR, RISC	MICROPROCESSOR, RISC	MICROPROCESSOR, RISC	MICROPROCESSOR, RISC	MICROPROCESSOR, RISC	MICROPROCESSOR, RISC
Maker	Motorola ( NXP )	-	-	Motorola ( NXP )	Motorola ( NXP )	Motorola ( NXP )	Motorola ( NXP )	Motorola ( NXP )	Motorola ( NXP )	Motorola ( NXP )

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Shortcut: E0 E1 E2 E3 E4 E5 E6 E7 E8 E9 EA EB EC ED EE EF EG EH EI EJ EK EL EM EN EO EP EQ ER ES ET EU EV EW EX EY EZ F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 FA FB FC FD FE FF FG FH FI FJ FK FL FM FN FO FP FQ FR FS FT FU FV FW FX FY FZ G0 G1 G2 G3 G4 G5 G6 G7 G8 G9 GA GB GC GD GE GF GG GH GI GJ GK GL GM GN GO GP GQ GR GS GT GU GV GW GX GZ H0 H1 H2 H3 H4 H5 H6 H7 H8 HA HB HC HD HE HF HG HH HI HJ HK HL HM HN HO HP HQ HR HS HT HU HV HW HX HY HZ I1 I2 I3 I4 I5 I6 I7 IA IB IC ID IE IF IG IH II IK IL IM IN IO IP IQ IR IS IT IU IV IW IX J0 J1 J2 J6 J7 JA JB JC JD JE JF JG JH JJ JK JL JM JN JP JQ JR JS JT JV JW JX JZ K0 K1 K2 K3 K4 K5 K6 K7 K8 K9 KA KB KC KD KE KF KG KH KI KJ KK KL KM KN KO KP KQ KR KS KT KU KV KW KX KY KZ

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