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AS7C512L-15JC

Description
Standard SRAM, 64KX8, 15ns, CMOS, PDSO32, 0.300 INCH, PLASTIC, SOJ-32
Categorystorage    storage   
File Size287KB,8 Pages
ManufacturerALSC [Alliance Semiconductor Corporation]
Download Datasheet Parametric View All

AS7C512L-15JC Overview

Standard SRAM, 64KX8, 15ns, CMOS, PDSO32, 0.300 INCH, PLASTIC, SOJ-32

AS7C512L-15JC Parametric

Parameter NameAttribute value
Is it lead-free?Contains lead
Is it Rohs certified?incompatible
MakerALSC [Alliance Semiconductor Corporation]
Parts packaging codeSOJ
package instructionSOJ, SOJ32,.34
Contacts32
Reach Compliance Codeunknown
ECCN code3A991.B.2.B
Maximum access time15 ns
I/O typeCOMMON
JESD-30 codeR-PDSO-J32
JESD-609 codee0
memory density524288 bit
Memory IC TypeSTANDARD SRAM
memory width8
Number of functions1
Number of ports1
Number of terminals32
word count65536 words
character code64000
Operating modeASYNCHRONOUS
Maximum operating temperature70 °C
Minimum operating temperature
organize64KX8
Output characteristics3-STATE
ExportableYES
Package body materialPLASTIC/EPOXY
encapsulated codeSOJ
Encapsulate equivalent codeSOJ32,.34
Package shapeRECTANGULAR
Package formSMALL OUTLINE
Parallel/SerialPARALLEL
Peak Reflow Temperature (Celsius)225
power supply5 V
Certification statusNot Qualified
Maximum standby current0.0002 A
Minimum standby current2 V
Maximum slew rate0.11 mA
Maximum supply voltage (Vsup)5.5 V
Minimum supply voltage (Vsup)4.5 V
Nominal supply voltage (Vsup)5 V
surface mountYES
technologyCMOS
Temperature levelCOMMERCIAL
Terminal surfaceTin/Lead (Sn/Pb)
Terminal formJ BEND
Terminal pitch1.27 mm
Terminal locationDUAL
Maximum time at peak reflow temperatureNOT SPECIFIED
High Performance
64K×8
CMOS SRAM
AS7C512
AS7C512L
®
64K×8 CMOS SRAM
Features
• Organization: 65,536 words × 8 bits
• High speed
- 12/15/20/25/35 ns address access time
- 3/4/5/6/8 ns output enable access time
• Low power consumption
- Active: 688 mW max (12 ns cycle)
- Standby: 27.5 mW max, CMOS I/O
4.25 mW max, CMOS I/O, L version
- Very low DC component in active power
• 2.0V data retention (L version)
• Equal access and cycle times
• Easy memory expansion with CE1, CE2, OE inputs
• TTL-compatible, three-state I/O
- 32-pin JEDEC standard packages
- 300 mil PDIP and SOJ
Socket compatible with 7C256 and 7C1024
- 525 mil SOIC
• ESD protection > 2000 volts
• Latch-up current > 200 mA
Logic block diagram
Vcc
GND
Pin arrangement
TSOP 8
×
20
OE
A10
CE1
I/O7
I/O6
I/O4
I/O5
I/O3
GND
I/O2
I/O1
I/O0
A0
A1
A2
A3
DIP, SOJ, SOIC
A0
A1
A2
A3
A4
A5
A6
A7
Row decoder
I/O7
Sense amp
AS7C512
32
31
30
29
28
27
26
25
24
23
22
21
20
19
18
17
Input buffer
256×256×8
Array
(524,288)
I/O0
WE
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
Column decoder
A A A A A A A A
8 9 10 11 12 13 14 15
Control
circuit
CE1
CE2
Selection guide
Maximum address access time
Maximum output enable access time
Maximum operating current
Maximum CMOS standby current
L
7C512-12
12
3
125
5.0
0.75
7C512-15
15
4
115
5.0
0.75
7C512-20
20
5
105
5.0
0.75
7C512-25
25
6
95
5.0
0.75
7C512-35
35
8
80
5.0
0.75
Unit
ns
ns
mA
mA
mA
ALLIANCE SEMICONDUCTOR
A11
A9
A8
A13
WE
CE2
A15
Vcc
NC
NC
A14
A12
A7
A6
A5
A4
OE
NC
NC
A14
A12
A7
A6
A5
A4
A3
A2
A1
A0
I/O0
I/O1
I/O2
GND
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
32
31
30
29
28
27
26
25
24
23
22
21
20
19
18
17
Vcc
A15
CE2
WE
A13
A8
A9
A11
OE
A10
CE1
I/O7
I/O6
I/O5
I/O4
I/O3
AS7C512
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