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Please help me find out what is wrong with this anti-shaking program. [Copy link]

library ieee;--Debounce delay 10ms
use ieee.std_logic_1164.all;
use ieee.std_logic_unsigned.all;
entity dou is
port(s,clk1k:in std_logic;
so:Put std_logic);
end;
architecture one of dou is
signal cout4 :std_logic_vector (3 downto 0);
signal f,en:std_logic;
begin
process(s)
begin
if s'event and s='1'then
f<='1';end if;
end process;
process(clk1k,f )
begin
if f='1' then
if clk1k'event and clk1k='1' then
if cout4=9 then cout4<=(others=>'0');en<='0';f<='0' ;
else cout4<=cout4+1;en<='1';end if;end if; else
cout4<=(others=>'0'); en<='0'; end if ; end process; process( en) constant a:std_logic:='0'; begin if en='1' then so<=a;else so<=s; end if; end process; end









Please see if there is any problem?

This post is from FPGA/CPLD

Latest reply

Looking at your program, you probably want to eliminate S, but you have latched the f signal with the S edge trigger. The clearing of f is after the count reaches 9. It seems that you have not effectively eliminated the jitter. It is best The best way is not to latch the s signal, but just perform the if judgment directly every CLK.  Details Published on 2010-12-13 21:07
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Can you post a flow chart? It’s too confusing to look at the code directly, and it’s not easy to understand your thinking. I usually use a state machine for keyboard scanning.
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else cout4<=cout4+1;en<='1';end if;end if; else cout4<=(others=>'0'); en<='0'; Are these two end ifs too early? Already? ?
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I think this program cannot play a role in eliminating jitter. Look at the following process: process(s) begin if s'event and s='1'then f<='1';end if; end process; as long as "s" If it is pressed, it will be regarded as a valid signal input. What if it is caused by jitter? When writing a dither program in VHDL, I personally think that a better idea is: Create several semaphores, such as a, b, c, assuming that the input is s and the output is so; under clock stimulation, a<=s;b <=a;c<=b; and so<=a and b and c and s; This plays a role in eliminating jitter. The above is for reference only, haha
This post is from FPGA/CPLD
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Looking at your program, you probably want to eliminate S, but you have latched the f signal with the S edge trigger. The clearing of f is after the count reaches 9. It seems that you have not effectively eliminated the jitter. It is best The best way is not to latch the s signal, but just perform the if judgment directly every CLK.
This post is from FPGA/CPLD

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