K7A403609B
K7A403209B
K7A401809B
128Kx36/x32 & 256Kx18 Synchronous SRAM
4Mb Sync. Pipelined Burst SRAM
Specification
100 TQFP with Pb & Pb-Free
(RoHS compliant)
INFORMATION IN THIS DOCUMENT IS PROVIDED IN RELATION TO SAMSUNG PRODUCTS,
AND IS SUBJECT TO CHANGE WITHOUT NOTICE.
NOTHING IN THIS DOCUMENT SHALL BE CONSTRUED AS GRANTING ANY LICENSE,
EXPRESS OR IMPLIED, BY ESTOPPEL OR OTHERWISE,
TO ANY INTELLECTUAL PROPERTY RIGHTS IN SAMSUNG PRODUCTS OR TECHNOLOGY.
ALL INFORMATION IN THIS DOCUMENT IS PROVIDED
ON AS "AS IS" BASIS WITHOUT GUARANTEE OR WARRANTY OF ANY KIND.
1. For updates or additional information about Samsung products, contact your nearest Samsung office.
2. Samsung products are not intended for use in life support, critical care, medical, safety equipment, or simi-
lar applications where Product failure could result in loss of life or personal or physical harm, or any military
or defense application, or any governmental procurement to which special terms or provisions may apply.
* Samsung Electronics reserves the right to change products or specification without notice.
-1-
Rev. 3.0 July 2006
K7A403609B
K7A403209B
K7A401809B
Document Title
128Kx36/x32 & 256Kx18 Synchronous SRAM
128Kx36 & 128Kx32 & 256Kx18-Bit Synchronous Pipelined Burst SRAM
Revision History
Rev. No
0.0
0.1
History
1. Initial draft
1. Changed DC parameters
Icc ; from 570mA to 490mA at -30,
from 520mA to 440mA at -27,
from 470mA to 400mA at -25,
from 440mA to 360mA at -22,
from 400mA to 330mA at -20,
from 370mA to 310mA at -18,
I
SB
; from 200mA
from 190mA
from 180mA
from 170mA
from 160mA
from 150mA
to
to
to
to
to
to
180mA at -30,
170mA at -27,
160mA at -25,
155mA at -22,
150mA at -20,
140mA at -18,
Draft Date
May. 15. 2001
June. 12. 2001
Remark
Preliminary
Preliminary
I
SB1
; from 100mA to 80mA
2. Input set-up(tAS,tSS,tDS,tWS,tADVS,tCSS) from 0.6ns to 0.7ns at -30
0.2
0.3
1. Delete Pass-Through
1. Changed Input set-up(tAS,tSS,tDS,tWS,tADVS,tCSS)
- from 0.8ns to 1.0ns at -25
- from 075ns to 0.8ns at -27
- from 0.7ns to 0.8ns at -30
1. Add x32 org and industrial range temperature
1. Final spec release
2. Changed Pin Capacitance
- Cin ; from 5pF to 4pF
- Cout ; from 7pF to 6pF
1. Remove tCYC 300/275/225MHz( -30/-27/-22)
1. Add Pb-free package
June. 25. 2001
July. 31. 2001
Preliminary
Preliminary
0.4
1.0
Aug. 11. 2001
Nov. 15. 2001
Preliminary
Final
2.0
3.0
Nov. 17. 2003
Jul. 03. 2006
Final
Final
-2-
Rev. 3.0 July 2006
K7A403609B
K7A403209B
K7A401809B
128Kx36/x32 & 256Kx18 Synchronous SRAM
4Mb SPB SRAM Ordering Information
Org.
256Kx18
128Kx32
128Kx36
3.3
VDD (V)
Speed (MHz)
250
200
250
200
250
200
Access Time (ns)
2.4
2.8
2.4
2.8
2.4
2.8
Part Number
K7A401809B-P(Q)
1
C(I)
2
25
K7A401809B-Q
3
C(I)20
K7A403209B-P(Q)
1
C(I)
2
25
K7A403209B-Q
3
C(I)20
K7A403609B-P(Q)
1
C(I)
2
25
K7A403609B-Q
3
C(I)20
RoHS Avail.
√
•
√
•
√
•
Note 1. P(Q) [Package type]: P-Pb Free, Q-Pb
2. C(I) [Operating Temperature]: C-Commercial, I-Industrial
3. Support only Pb package parts at this frequency. To use Pb-Free package, use faster frequency parts.
-3-
Rev. 3.0 July 2006
K7A403609B
K7A403209B
K7A401809B
128Kx36/x32 & 256Kx18 Synchronous SRAM
128Kx36 & 128Kx32 & 256Kx18-Bit Synchronous Pipelined Burst SRAM
FEATURES
• Synchronous Operation.
• 2 Stage Pipelined operation with 4 Burst.
• On-Chip Address Counter.
• Self-Timed Write Cycle.
• On-Chip Address and Control Registers.
• V
DD
= 3.3V+0.3V/-0.165V Power Supply.
• V
DDQ
Supply Voltage 3.3V+0.3V/-0.165V for 3.3V I/O
or 2.5V+0.4V/-0.125V for 2.5V I/O.
• 5V Tolerant Inputs Except I/O Pins.
• Byte Writable Function.
• Global Write Enable Controls a full bus-width write.
• Power Down State via ZZ Signal.
• LBO Pin allows a choice of either a interleaved burst or a linear
burst.
• Three Chip Enables for simple depth expansion with No Data Cont-
nention ; 2cycle Enable, 1cycle Disable.
• Asynchronous Output Enable Control.
• ADSP, ADSC, ADV Burst Control Pins.
• TTL-Level Three-State Output.
• 100-TQFP-1420A .
• Operating in commercial and industrial temperature range.
GENERAL DESCRIPTION
The K7A403609B, K7A403209B and K7A401809B are
4,718,592-bit Synchronous Static Random Access Memory
designed for high performance second level cache of Pen-
tium and Power PC based System.
It is organized as 128K(256K) words of 36(18) bits and inte-
grates address and control registers, a 2-bit burst address
counter and added some new functions for high perfor-
mance cache RAM applications; GW, BW, LBO, ZZ. Write
cycles are internally self-timed and synchronous.
Full bus-width write is done by GW, and each byte write is
performed by the combination of WEx and BW when GW is
high. And with CS
1
high, ADSP is blocked to control signals.
Burst cycle can be initiated with either the address status
processor(ADSP) or address status cache controller(ADSC)
inputs. Subsequent burst addresses are generated inter-
nally in the system′s burst sequence and are controlled by
the burst address advance(ADV) input.
LBO pin is DC operated and determines burst sequence(lin-
ear or interleaved).
ZZ pin controls Power Down State and reduces Stand-by
current regardless of CLK.
The K7A403609B, K7A403209B and K7A401809B are fab-
ricated using SAMSUNG′s high performance CMOS tech-
nology and is available in a 100pin TQFP package. Multiple
power and ground pins are utilized to minimize ground
bounce.
FAST ACCESS TIMES
PARAMETER
Cycle Time
Clock Access Time
Output Enable Access Time
Symbol
tCYC
tCD
tOE
-25
4.0
2.4
2.4
-20
5.0
2.8
2.8
Unit
ns
ns
ns
LOGIC BLOCK DIAGRAM
CLK
LBO
CONTROL
REGISTER
ADV
ADSC
BURST CONTROL
LOGIC
BURST
ADDRESS
A′0~A′1
COUNTER
A0~A1
128Kx36/32 , 256Kx18
MEMORY
ARRAY
ADSP
A0~A16
or A0~A17
ADDRESS
REGISTER
A2~A16
or A2~A17
CS1
CS2
CS2
GW
BW
WEx
(x=a,b,c,d or a,b)
OE
ZZ
DQa0 ~ DQd7
DQPa ~ DQPd
DATA-IN
REGISTER
CONTROL
REGISTER
or DQa0 ~ DQb7
DQPa ~ DQPb
CONTROL
LOGIC
OUTPUT
REGISTER
BUFFER
36/32 or 18
-4-
Rev. 3.0 July 2006
K7A403609B
K7A403209B
K7A401809B
PIN CONFIGURATION
(TOP VIEW)
128Kx36/x32 & 256Kx18 Synchronous SRAM
ADSC
WEb
WEa
WEc
ADSP
WEd
CS
2
ADV
83
CLK
CS
1
CS
2
V
DD
GW
V
SS
BW
OE
A
6
A
7
A
8
82
100
99
98
97
96
95
94
93
92
91
90
89
88
87
86
85
84
81
A
9
31
32
33
34
35
36
37
38
39
40
41
42
43
44
45
46
47
48
49
LBO
V
SS
V
DD
A
5
A
4
A
3
A
2
A
1
A
0
A
10
A
12
A
13
A
14
A
15
N.C.
N.C.
N.C.
N.C.
PIN NAME
SYMBOL
A
0
- A
16
PIN NAME
Address Inputs
TQFP PIN NO.
SYMBOL
V
DD
V
SS
N.C.
DQa
0
~a
7
DQb
0
~b
7
DQc
0
~c
7
DQd
0
~d
7
DQPa~P
d
/NC
V
DDQ
V
SSQ
PIN NAME
Power Supply(+3.3V)
Ground
No Connect
Data Inputs/Outputs
TQFP PIN NO.
15,41,65,91
17,40,67,90
14,16,38,39,42,43,66
52,53,56,57,58,59,62,63
68,69,72,73,74,75,78,79
2,3,6,7,8,9,12,13
18,19,22,23,24,25,28,29
51,80,1,30
4,11,20,27,54,61,70,77
5,10,21,26,55,60,71,76
32,33,34,35,36,37
44,45,46,47,48,49
50,81,82,99,100
83
Burst Address Advance
Address Status Processor 84
Address Status Controller 85
89
Clock
98
Chip Select
97
Chip Select
92
Chip Select
93,94,95,96
Byte Write Inputs
Output Enable
Global Write Enable
Byte Write Enable
Power Down Input
Burst Mode Control
86
88
87
64
31
ADV
ADSP
ADSC
CLK
CS
1
CS
2
CS
2
WEx
(x=a,b,c,d)
OE
GW
BW
ZZ
LBO
A
11
Output Power Supply
(2.5V or 3.3V)
Output Ground
A
16
50
DQPc/NC
DQc
0
DQc
1
V
DDQ
V
SSQ
DQc
2
DQc
3
DQc
4
DQc
5
V
SSQ
V
DDQ
DQc
6
DQc
7
N.C.
V
DD
N.C.
V
SS
DQd
0
DQd
1
V
DDQ
V
SSQ
DQd
2
DQd
3
DQd
4
DQd
5
V
SSQ
V
DDQ
DQd
6
DQd
7
DQPd/NC
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
100 Pin TQFP
(20mm x 14mm)
K7A403609B(128Kx36)
K7A403209B(128Kx32)
80
79
78
77
76
75
74
73
72
71
70
69
68
67
66
65
64
63
62
61
60
59
58
57
56
55
54
53
52
51
DQPb/NC
DQb
7
DQb
6
V
DDQ
V
SSQ
DQb
5
DQb
4
DQb
3
DQb
2
V
SSQ
V
DDQ
DQb
1
DQb
0
V
SS
N.C.
V
DD
ZZ
DQa
7
DQa
6
V
DDQ
V
SSQ
DQa
5
DQa
4
DQa
3
DQa
2
V
SSQ
V
DDQ
DQa
1
DQa
0
DQPa/NC
-5-
Rev. 3.0 July 2006
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