M27C800
8 Mbit (1Mb x8 or 512Kb x16) UV EPROM and OTP EPROM
s
5V
±
10% SUPPLY VOLTAGE in READ
OPERATION
ACCESS TIME: 50ns
BYTE-WIDE or WORD-WIDE
CONFIGURABLE
8 Mbit MASK ROM REPLACEMENT
1
1
42
42
s
s
s
s
LOW POWER CONSUMPTION
– Active Current 70mA at 8MHz
– Stand-by Current 50µA
FDIP42W (F)
PDIP42 (B)
s
s
s
PROGRAMMING VOLTAGE: 12.5V
±
0.25V
PROGRAMMING TIME: 50µs/word
ELECTRONIC SIGNATURE
– Manufacturer Code: 20h
– Device Code: B2h
PLCC44 (K)
1
44
SO44 (M)
DESCRIPTION
The M27C800 is an 8 Mbit EPROM offered in the
two ranges UV (ultra violet erase) and OTP (one
time programmable). It is ideally suited for micro-
processor systems requiring large data or program
storage. It is organised as either 1 Mwords of 8 bit
or 512 Kwords of 16 bit. The pin-out is compatible
with the most common 8 Mbit Mask ROM.
The FDIP42W (window ceramic frit-seal package)
has a transparent lid which allows the user to ex-
pose the chip to ultraviolet light to erase the bit pat-
tern.
A new pattern can then be written rapidly to the de-
vice by following the programming procedure.
For applications where the content is programmed
only one time and erasure is not required, the
M27C800 is offered in PDIP42, PLCC44 and
SO44 packages.
Figure 1. Logic Diagram
VCC
19
A0-A18
15
Q15A–1
Q0-Q14
E
G
BYTEVPP
M27C800
VSS
AI01593
January 2000
1/17
M27C800
Figure 2A. DIP Connections
A18
A17
A7
A6
A5
A4
A3
A2
A1
A0
E
VSS
G
Q0
Q8
Q1
Q9
Q2
Q10
Q3
Q11
42
1
41
2
40
3
39
4
38
5
37
6
36
7
35
8
34
9
33
10
M27C800
32
11
31
12
30
13
29
14
28
15
27
16
17
26
18
25
19
24
20
23
21
22
AI01594
Figure 2B. LCC Connections
NC
A8
A9
A10
A11
A12
A13
A14
A15
A16
BYTEVPP
VSS
Q15A–1
Q7
Q14
Q6
Q13
Q5
Q12
Q4
VCC
A4
A3
A2
A1
A0
E
VSS
G
Q0
Q8
Q1
A5
A6
A7
A17
A18
VSS
NC
A8
A9
A10
A11
1 44
A12
A13
A14
A15
A16
BYTEVPP
VSS
Q15A–1
Q7
Q14
Q6
12
M27C800
34
23
Q9
Q2
Q10
Q3
Q11
NC
VCC
Q4
Q12
Q5
Q13
AI02042
Figure 2C. SO Connections
NC
A18
A17
A7
A6
A5
A4
A3
A2
A1
A0
E
VSS
G
Q0
Q8
Q1
Q9
Q2
Q10
Q3
Q11
1
44
43
2
42
3
41
4
40
5
39
6
38
7
37
8
36
9
35
10
34
11
M27C800
33
12
32
13
31
14
30
15
29
16
17
28
18
27
19
26
20
25
21
24
22
23
AI01595
Table 1. Signal Names
A0-A18
NC
NC
A8
A9
A10
A11
A12
A13
A14
A15
A16
BYTEVPP
VSS
Q15A–1
Q7
Q14
Q6
Q13
Q5
Q12
Q4
VCC
Address Inputs
Data Outputs
Data Outputs
Data Output / Address Input
Chip Enable
Output Enable
Byte Mode / Program Supply
Supply Voltage
Ground
Not Connected Internally
Q0-Q7
Q8-Q14
Q15A–1
E
G
BYTEV
PP
V
CC
V
SS
NC
2/17
M27C800
Table 2. Absolute Maximum Ratings
(1)
Symbol
T
A
T
BIAS
T
STG
V
IO (2)
V
CC
V
A9 (2)
V
PP
Parameter
Ambient Operating Temperature
(3)
Temperature Under Bias
Storage Temperature
Input or Output Voltage (except A9)
Supply Voltage
A9 Voltage
Program Supply Voltage
Value
–40 to 125
–50 to 125
–65 to 150
–2 to 7
–2 to 7
–2 to 13.5
–2 to 14
Unit
°C
°C
°C
V
V
V
V
Note: 1. Except for the rating ”Operating Temperature Range”, stresses above those listed in the Table ”Absolute Maximum Ratings” may
cause permanent damage to the device. These are stress ratings only and operation of the device at these or any other conditions
above those indicated in the Operating sections of this specification is not implied. Exposure to Absolute Maximum Rating condi-
tions for extended periods may affect device reliability. Refer also to the STMicroelectronics SURE Program and other relevant qual-
ity documents.
2. Minimum DC voltage on Input or Output is –0.5V with possible undershoot to –2.0V for a period less than 20ns. Maximum DC
voltage on Output is V
CC
+0.5V with possible overshoot to V
CC
+2V for a period less than 20ns.
3. Depends on range.
Table 3. Operating Modes
Mode
Read Word-wide
Read Byte-wide Upper
Read Byte-wide Lower
Output Disable
Program
Verify
Program Inhibit
Standby
Electronic Signature
E
V
IL
V
IL
V
IL
V
IL
V
IL
Pulse
V
IH
V
IH
V
IH
V
IL
G
V
IL
V
IL
V
IL
V
IH
V
IH
V
IL
V
IH
X
V
IL
BYTEV
PP
V
IH
V
IL
V
IL
X
V
PP
V
PP
V
PP
X
V
IH
A9
X
X
X
X
X
X
X
X
V
ID
Q15A–1
Data Out
V
IH
V
IL
Hi-Z
Data In
Data Out
Hi-Z
Hi-Z
Code
Q14-Q8
Data Out
Hi-Z
Hi-Z
Hi-Z
Data In
Data Out
Hi-Z
Hi-Z
Codes
Q7-Q0
Data Out
Data Out
Data Out
Hi-Z
Data In
Data Out
Hi-Z
Hi-Z
Codes
Note: X = V
IH
or V
IL
, V
ID
= 12V
±
0.5V.
Table 4. Electronic Signature
Identifier
Manufacturer’s Code
Device Code
A0
V
IL
V
IH
Q15
and
Q7
0
1
Q14
and
Q6
0
0
Q13
and
Q5
1
1
Q12
and
Q4
0
1
Q11
and
Q3
0
0
Q10
and
Q2
0
0
Q9
and
Q1
0
1
Q8
and
Q0
0
0
Hex Data
20h
B2h
3/17
M27C800
Table 5. AC Measurement Conditions
High Speed
Input Rise and Fall Times
Input Pulse Voltages
Input and Output Timing Ref. Voltages
≤
10ns
0 to 3V
1.5V
Standard
≤
20ns
0.4V to 2.4V
0.8V and 2V
Figure 3. AC Testing Input Output Waveform
Figure 4. AC Testing Load Circuit
1.3V
High Speed
3V
1.5V
0V
DEVICE
UNDER
TEST
2.0V
0.8V
AI01822
1N914
3.3kΩ
Standard
2.4V
OUT
CL
0.4V
CL = 30pF for High Speed
CL = 100pF for Standard
CL includes JIG capacitance
AI01823B
DEVICE OPERATION
The operating modes of the M27C800 are listed in
the Operating Modes Table. A single power supply
is required in the read mode. All inputs are TTL
compatible except for V
PP
and 12V on A9 for the
Electronic Signature.
Read Mode
The M27C800 has two organisations, Word-wide
and Byte-wide. The organisation is selected by the
signal level on the BYTEV
PP
pin. When BYTEV
PP
is at V
IH
the Word-wide organisation is selected
and the Q15A–1 pin is used for Q15 Data Output.
When the BYTEV
PP
pin is at V
IL
the Byte-wide or-
ganisation is selected and the Q15A–1 pin is used
for the Address Input A–1. When the memory is
logically regarded as 16 bit wide, but read in the
Byte-wide organisation, then with A–1 at V
IL
the
lower 8 bits of the 16 bit data are selected and with
A–1 at V
IH
the upper 8 bits of the 16 bit data are
selected.
The M27C800 has two control functions, both of
which must be logically active in order to obtain
data at the outputs. In addition the Word-wide or
Byte- wide organisation must be selected.
Chip Enable (E) is the power control and should be
used for device selection. Output Enable (G) is the
output control and should be used to gate data to
the output pins independent of device selection.
Assuming that the addresses are stable, the ad-
dress access time (t
AVQV
) is equal to the delay
from E to output (t
ELQV
). Data is available at the
output after a delay of t
GLQV
from the falling edge
of G, assuming that E has been low and the ad-
dresses have been stable for at least t
AVQV
-t
GLQV
.
4/17
M27C800
Table 6. Capacitance
(1)
(T
A
= 25
°C,
f = 1 MHz)
Symbol
C
IN
C
OUT
Parameter
Input Capacitance (except BYTEV
PP
)
Input Capacitance (BYTEV
PP
)
Output Capacitance
Test Condit ion
V
IN
= 0V
V
IN
= 0V
V
OUT
= 0V
Min
Max
10
120
12
Unit
pF
pF
pF
Note: 1. Sampled only, not 100% tested.
Table 7. Read Mode DC Characteristics
(1)
(T
A
= 0 to 70
°C
or –40 to 85
°C;
V
CC
= 5V
±
5% or 5V
±
10%; V
PP
= V
CC
)
Symbol
I
LI
I
LO
Parameter
Input Leakage Current
Output Leakage Current
Test Condition
0V
≤
V
IN
≤
V
CC
0V
≤
V
OUT
≤
V
CC
E = V
IL
, G = V
IL
,
I
OUT
= 0mA, f = 8MHz
Supply Current
E = V
IL
, G = V
IL
,
I
OUT
= 0mA, f = 5MHz
Supply Current (Standby) TTL
Supply Current (Standby) CMOS
Program Current
Input Low Voltage
Input High Voltage
Output Low Voltage
Output High Voltage TTL
I
OL
= 2.1mA
I
OH
= –400µA
2.4
E = V
IH
E > V
CC
– 0.2V
V
PP
= V
CC
–0.3
2
50
1
50
10
0.8
V
CC
+ 1
0.4
mA
mA
µA
µA
V
V
V
V
Min
Max
±1
±10
70
Unit
µA
µA
mA
I
CC
I
CC1
I
CC2
I
PP
V
IL
V
IH (2)
V
OL
V
OH
Note: 1. V
CC
must be applied simultaneously with or before V
PP
and removed simultaneously or after V
PP
.
2. Maximum DC voltage on Output is V
CC
+ 0.5V.
Standby Mode
The M27C800 has a standby mode which reduces
the supply current from 50mA to 100µA. The
M27C800 is placed in the standby mode by apply-
ing a CMOS high signal to the E input. When in the
standby mode, the outputs are in a high imped-
ance state, independent of the G input.
5/17
NXP MCU
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