IR3523
DATASHEET
XPHASE3
TM
DUAL OUTPUT CONTROL IC
DESCRIPTION
The IR3523 Control IC provides a full featured and flexible way to implement a complete dual output DDR &
CPU VTT multiphase power solution for Intel VR11.1 motherboards. Each output interfaces with any number of
TM
xPHASE3
Phase ICs each driving and monitoring a single phase. Output 1 includes a 3 bit VR11.x VID, 1.1V
boot voltage and droop to implement the CPU VTT rail which is typically 1 phase. Output 2 includes a 3 bit VID for
TM
margining and supports any number of phases and DDR DIMM modules. The
xPHASE3
architecture results in a
power supply that is smaller, less expensive, and easier to design while providing higher efficiency than
conventional approaches.
INDEPENDENT FEATURES FOR BOTH OUTPUT 1 & 2
•
•
•
•
•
•
•
•
•
Enable Input
Power Good (PG) Output
0.5% overall system set point accuracy
Programmable Softstart
High speed error amplifier with wide bandwidth of 30MHz and fast slew rate of 12V/us
Remote sense amplifier provides differential sensing and requires less than 50uA bias current
Programmable over current threshold triggers constant converter output current limit during start-up and
hiccup protection during normal operation
Over voltage condition communicated to phase ICs by IIN (ISHARE) and system by ROSC/OVP pins
Detection and protection of open remote sense lines
OUTPUT 1 ADDITIONAL FEATURES
•
•
•
•
•
3 bit Intel VR11.x VID (VID4, VID3, VID2)
Programmable VID offset
1.1 V Boot Voltage
Programmable output impedance
Programmable VID-on-the-Fly Slew Rate
OUTPUT 2 ADDITIONAL FEATURES
•
•
3 bit VID provides 1.5 V with ±150mV margining
Programmable VID-on-the-Fly Slew Rate
FEATURES SHARED BY BOTH OUTPUTS 1 & 2
•
•
•
•
Programmable per phase switching frequency of 250kHz to 1.5MHz
Daisy-chain digital phase timing provides accurate phase interleaving without external components
Gate Drive and IC bias linear regulator control with programmable output voltage and UVLO
Over voltage signal to system with over voltage detection during powerup and normal operation
ORDERING INFORMATION
Device
IR3523MTRPBF
* IR3523MPBF
* Samples only
Package
40 Lead MLPQ (6 x 6 mm body)
40 Lead MLPQ (6 x 6 mm body)
Order Quantity
3000 per reel
100 piece strips
Page 1 of 37
June 20, 2008
IR3523
APPLICATION CIRCUIT
12V
Q1
RVCCLFB1
RVCCLDRV
RVCCLFB2
CVCCL
4.7uF
12V
VCCL
To Pow er Stage
To Phase IC
VCCL & GATE
DRIVE BIAS
PG2
VID2_0
VID2_1
34
40
39
38
37
36
35
33
32
31
PHSIN
PHSOUT
CLKOUT
VID2_2
3 w ire Digital
Daisy Chain Bus
to Phase ICs
VCCLDRV
VCCLFB
VID2_2
VID2_1
VID2_0
PG2
VCCL
VID1_4
VID1_3
VID1_2
ENABLE 2
ENABLE 1
CSS/DEL2
CVDAC1
1
2
3
4
5
6
7
RVDAC2
8
9
10
PHSOUT
CLKOUT
PHSIN
VID1_4
VID1_3
VID1_2
ENABLE2
ENABLE1
IIN2
SS/DEL2
VDAC2
OCSET2
VOSNS2+
VOUT2
NC
LGND
PG1
30
29
28
27
26
ROSC
25
24
RVDAC1
23
22
21
CDRP1
RDRP1
ROCSET1
CSS/DEL1
CVDAC1
PG1
OVP FLAG
IR3523
CONTROL
IC
ROSC/OVP
VDRP1
IIN1
SS/DEL1
VDAC1
OCSET1
ISHARE1
VDAC1
EAOUT1
ROCSET2
VOUT1
EAOUT2
FB2
NC
VOSNS1+
VONSN1-
VOSNS2-
EAOUT1
FB1
NC
3 Wire Analog
Control Bus to
Output 1 Phase
ICs
11
12
13
14
15
16
17
18
19
RCP2
CCP21
RFB22
RFB21
CFB2
CFB1
20
RFB12
RCP1
CCP11
RTHERMISTOR1
CCP22
RFB11
CCP12
Load Line NTC
Thermistor; Locate
close to Output 1
Pow er Stage
To Output 2
Remote Sense
To Output 2
Remote
Sense
VOUT2 SENSE +
VOUT2 SENSE -
RFB13
VOUT1 SENSE +
VOUT1 SENSE -
EAOUT2
VREF2
ISHARE2
3 Wire Analog
Control Bus to
Output 2 Phase
ICs
Figure 1 – IR3523 Application Circuit
PIN DESCRIPTION
PIN#
1-3
4
PIN SYMBOL
VID1_4,
VID1_3, VID1_2
ENABLE2
PIN DESCRIPTION
VID inputs for Output 1
Enable input. A logic low applied to this pin puts output 2 into fault mode. A
logic high signal on this pin enables output 2. Do not float as the logic state will
be undefined.
Enable input. A logic low applied to this pin puts output 2 into fault mode. A
logic high signal on this pin enables output 2. Do not float as the logic state will
be undefined.
Output 2 average current input from the output 2 phase IC(s). This pin is also
used to communicate over voltage condition to the output 2 phase ICs.
Programs output 2 startup and over current protection delay timing. Connect an
external capacitor to LGND to program.
Output 2 reference voltage. Connect an external RC network to LGND to
provide compensation for the internal buffer amplifier
Programs the output 2 constant converter output current limit and hiccup over-
current threshold through an external resistor tied to VDAC2 and an internal
current source from this pin. Over-current protection can be disabled by
connecting a resistor from this pin to VDAC2 to program the threshold higher
than the possible signal into the IIN pin from the phase ICs but no greater than
5V (do not float this pin as improper operation will occur).
Output 2 error amplifier output
No Connection
5
ENABLE1
6
7
8
9
IIN2
SS/DEL2
VDAC2
OCSET2
10
11,20,30
EAOUT2
NC
Page 2 of 37
June 20, 2008
IR3523
PIN#
12
13
14
15
16
17
18
19
21
22
PIN SYMBOL
FB2
VOUT2
VOSEN2+
VOSEN2-
VOSEN1-
VOSEN1+
VOUT1
FB1
EAOUT1
OCSET1
PIN DESCRIPTION
Output 2 Error Amplifier inverting input
Output 2 remote sense amplifier output.
Output 2 remote sense amplifier input. Connect to output at the load.
Output 2 remote sense amplifier input. Connect to ground at the load.
Output 1 remote sense amplifier input. Connect to ground at the load.
Output 1 remote sense amplifier input. Connect to output at the load.
Output 1 remote sense amplifier output.
Inverting input to the output 1 Error Amplifier
Output 1 error amplifier output
Programs the output 1 constant converter output current limit and hiccup over-
current threshold through an external resistor tied to VDAC1 and an internal
current source from this pin. Over-current protection can be disabled by
connecting a resistor from this pin to VDAC1 to program the threshold higher
than the possible signal into the IIN pin from the phase ICs but no greater than
5V (do not float this pin as improper operation will occur).
Output 1 reference voltage programmed by the VID inputs and error amplifier
non-inverting input. Connect an external RC network to LGND to program
dynamic VID slew rate and provide compensation for the internal buffer
amplifier.
Programs output 1 startup and over current protection delay timing. Connect an
external capacitor to LGND to program.
Output 1 average current input from the output 1 phase IC(s). This pin is also
used to communicate over voltage condition to phase ICs.
Output 1 Buffered IIN signal. Connect an external RC network to FB1 to
program converter output impedance.
Connect a resistor to LGND to program oscillator frequency and OCSET,
VDAC1 and VREF2 bias currents. Oscillator frequency equals switching
frequency per phase. The pin voltage is 0.6V during normal operation and
higher than 1.6V if over-voltage condition is detected.
Open collector output. Asserted when Output 1 is regulated.
Local Ground for internal circuitry and IC substrate connection.
Clock output at switching frequency multiplied by phase number. Connect to
CLKIN pins of phase ICs.
Phase clock output at switching frequency per phase. Connect to PHSIN pin of
the first phase IC.
Feedback input of phase clock. Connect to PHSOUT pin of the last phase IC.
Output of the voltage regulator, and power input for clock oscillator circuitry.
Connect a decoupling capacitor to LGND.
Non-inverting input of the voltage regulator error amplifier. Output voltage of the
regulator is programmed by the resistor divider connected to VCCL.
Output of the VCCL regulator error amplifier to control external transistor. The
pin senses the converter input voltage through a resistor.
Open collector output. Asserted when Output 2 output is regulated.
VID inputs for Output 2
23
VDAC1
24
25
26
27
SS/DEL1
IIN1
VDRP1
ROSC/OVP
28
29
31
32
33
34
35
36
37
38, 39,
40
PG1
LGND
CLKOUT
PHSOUT
PHSIN
VCCL
VCCLFB
VCCLDRV
PG2
VID2_0,
VID2_1, VID2_2
Page 3 of 37
June 20, 2008
IR3523
ABSOLUTE MAXIMUM RATINGS
Absolute maximum ratings indicate sustained limits beyond which damage to the device may occur. All voltages are
absolute voltages referenced to the LGND pin.
Operating Junction Temperature……………..0 to 150 C
o
o
Storage Temperature Range………………….-65 C to 150 C
ESD Rating………………………………………HBM Class 1C JEDEC Standard
MSL Rating………………………………………2
o
Reflow Temperature…………………………….260 C
PIN #
1
2
3
4
5
6
7
8
9
10
12
13
14
15
16
17
18
19
21
22
23
24
25
26
27
28
29
31
32
33
34
35
36
37
38
39
40
PIN NAME
VID1_4
VID1_3
VID1_2
ENABLE2
ENABLE1
IIN2
SS/DEL2
VDAC2
OCSET2
EAOUT2
FB2
VOUT2
VOSEN2+
VOSEN2-
VOSEN1-
VOSEN1+
VOUT1
FB1
EAOUT1
OCSET1
VDAC1
SS/DEL1
IIN1
VDRP1
ROSC/OVP
PG1
LGND
CLKOUT
PHSOUT
PHSIN
VCCL
VCCLFB
VCCLDRV
PG2
VID2_0
VID2_1
VID2_2
V
MAX
8V
8V
8V
3.5V
3.5V
8V
8V
3.5V
8V
8V
8V
8V
8V
1.0V
1.0V
8V
8V
8V
8V
8V
3.5V
8V
8V
8V
8V
8V
n/a
8V
8V
8V
8V
3.5V
10V
8V
8V
8V
8V
V
MIN
-0.3V
-0.3V
-0.3V
-0.3V
-0.3V
-0.3V
-0.3V
-0.3V
-0.3V
-0.3V
-0.3V
-0.5V
-0.5V
-0.5V
-0.5V
-0.5V
-0.5V
-0.3V
-0.3V
-0.3V
-0.3V
-0.3V
-0.3V
-0.3V
-0.5V
-0.3V
n/a
-0.3V
-0.3V
-0.3V
-0.3V
-0.3V
-0.3V
-0.3V
-0.3V
-0.3V
-0.3V
I
SOURCE
1mA
1mA
1mA
1mA
1mA
5mA
1mA
1mA
1mA
25mA
1mA
5mA
5mA
5mA
5mA
5mA
5mA
1mA
25mA
1mA
1mA
1mA
5mA
35mA
1mA
1mA
20mA
100mA
10mA
1mA
1mA
1mA
1mA
1mA
1mA
1mA
1mA
I
SINK
1mA
1mA
1mA
1mA
1mA
1mA
1mA
1mA
1mA
10mA
1mA
25mA
1mA
1mA
1mA
1mA
25mA
1mA
10mA
1mA
1mA
1mA
1mA
1mA
1mA
20mA
1mA
100mA
10mA
1mA
20mA
1mA
50mA
20mA
1mA
1mA
1mA
o
Page 4 of 37
June 20, 2008
IR3523
RECOMMENDED OPERATING CONDITIONS FOR RELIABLE OPERATION WITH MARGIN
o
o
4.75V
≤
VCCL
≤
7.5V, -0.3V
≤
VOSEN-x
≤
0.3V, 0 C
≤
T
J
≤
100 C, 7.75 k
≤
ROSC
≤
50 k , CSS/DELx = 0.1uF
ELECTRICAL CHARACTERISTICS
The electrical characteristics involve the spread of values guaranteed within the recommended operating
conditions (unless otherwise specified). Typical values represent the median values, which are related to 25°C.
PARAMETER
System Set Point Accuracy
Deviation from Table 1 for Output
1 and deviation from Table 2 for
Output 2 per test circuit in Figure
4a and 4b, respectively
TEST CONDITION
Output 2 and Output 1
Output 2 at 1.8V (only)
MIN
-0.5
-1.5
TYP
MAX
0.5
1.5
UNIT
%
%
VIDx Interface
Input Thresholds
Increasing
Decreasing (VID2_0 and VID2_1 Only)
Hysteresis (VID2_0 and VID2_1 Only)
0.85
550
190
100
-10%
0.575
I(CLKOUT)= -10 mA, measure V(VCCL) –
V(CLKOUT).
I(CLKOUT)= 10 mA
I(PHSOUT)= -1 mA, measure V(VCCL) –
V(PHSOUT)
I(PHSOUT)= 1 mA
Compare to V(VCCL)
V(VDRP) – V(IIN), 0.5V
≤
V(IIN)
≤
3.3V
0.5V
≤
V(IIN1)
≤
3.3V
0.5V
≤
V(IIN1)
≤
3.3V
Note 1
Note 1
.95
650
300
175
See
Figure 2
0.600
1.05
750
410
250
+10%
0.625
1
1
1
1
70
8
30
0.6
V
mV
mV
k
kHz
V
V
V
V
V
%
mV
mA
mA
MHz
V/µs
µA
MHz
mV
mA
mA
V/us
uA
uA
mV
V
µA
µA
Pull-Down Resistance
Oscillator
PHSOUT Frequency
ROSC Voltage
CLKOUT High Voltage
CLKOUT Low Voltage
PHSOUT High Voltage
PHSOUT Low Voltage
PHSIN Threshold Voltage
30
-8
2
0.2
50
0
0.4
8
4.7
0
6.4
0
1
12
4
30
30
0.5
VDRP1 Buffer Amplifiers
Input Offset Voltage
Source Current
Sink Current
Unity Gain Bandwidth
Slew Rate
IIN Bias Current
Unity Gain Bandwidth
Input Offset Voltage
Source Current
Sink Current
Slew Rate
VOSEN+ Bias Current
VOSEN- Bias Current
Low Voltage
High Voltage
VDAC1 & VDAC2 Outputs
Source Currents
Sink Currents
-1
Note 1
0.5V≤ V(VOSENx+) - V(VOSENx-)
≤
1.6V,
Note 2
0.5V≤ V(VOSENx+) - V(VOSENx-)
≤
1.6V
0.5V≤ V(VOSENx+) - V(VOSENx-)
≤
1.6V
0.5V≤ V(VOSENx+) - V(VOSENx-)
≤
1.6V,
Note 1
0.5 V < V(VOSENx+) < 1.6V
-0.3V
≤
VOSENx-
≤
0.3V, All VID Codes
V(VCCL) = 7V
V(VCCL) – V(VOUTx)
Includes I(OCSET)
Includes I(OCSET)
3.0
-3
0.5
2
2
1
9.0
3
1.7
18
8
50
50
250
1
+8%
+11%
Remote Sense Differential Amplifiers
-8%
-11%
3000*Vrosc(
V)/
ROSC(k )
1000*Vrosc
V)/
ROSC(k )
Page 5 of 37
June 20, 2008
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