X4325V8-2.7 datasheet, PDF - EEWORLD Datasheet

®

X4323, X4325

32k, 4k x 8 Bit

Data Sheet

May 25, 2006

FN8122.1

CPU Supervisor with 32k EEPROM

FEATURES

• Selectable watchdog timer

• Low V

CC

detection and reset assertion

—Four standard reset threshold voltages

—Adjust low V

CC

reset threshold voltage using

special programming sequence

—Reset signal valid to V

CC

= 1V

• Low power CMOS

—<20µA max standby current, watchdog on

—<1µA standby current, watchdog off

—3mA active current

• 32Kbits of EEPROM

—64-byte page write mode

—Self-timed write cycle

—5ms write cycle time (typical)

• Built-in inadvertent write protection

—Power-up/power-down protection circuitry

—Block Lock (1, 2, 4, 8 pages, all, none)

• 400kHz 2-wire interface

• 2.7V to 5.5V power supply operation

• Available packages

—8 Ld SOIC

—8 Ld TSSOP

• Pb-free plus anneal available (RoHS compliant)

DESCRIPTION

The X4323, X4325 combines four popular functions,

Power-on Reset Control, Watchdog Timer, Supply Volt-

age Supervision, and Serial EEPROM Memory in one

package. This combination lowers system cost,

reduces board space requirements, and increases

reliability.

Applying power to the device activates the power-on

reset circuit which holds RESET/RESET active for a

period of time. This allows the power supply and oscilla-

tor to stabilize before the processor can execute code.

The Watchdog Timer provides an independent protec-

tion mechanism for microcontrollers. When the micro-

controller fails to restart a timer within a selectable time

out interval, the device activates the RESET/RESET

signal. The user selects the interval from three preset

values. Once selected, the interval does not change,

even after cycling the power.

The device’s low V

CC

detection circuitry protects the

user’s system from low voltage conditions, resetting the

system when V

CC

falls below the set minimum V

CC

trip

point. RESET/RESET is asserted until V

CC

returns to

proper operating level and stabilizes. Four industry

standard V

TRIP

thresholds are available, however, Inter-

sil’s unique circuits allow the threshold to be repro-

grammed to meet custom requirements or to fine-tune

the threshold for applications requiring higher precision.

BLOCK DIAGRAM

Watchdog Transition

Detector

WP

SDA

Data

Register

Command

Decode &

Control

Logic

V

CC

Threshold

Reset logic

Block Lock Control

Protect Logic

Status

Register

EEPROM Array

RESET (X4323)

RESET (X4325)

Reset &

Watchdog

Timebase

4kb

Watchdog

Timer Reset

SCL

S0

S1

V

CC

V

TRIP

+

-

Power-on and

Low Voltage

Reset

Generation

1

CAUTION: These devices are sensitive to electrostatic discharge; follow proper IC Handling Procedures.

1-888-INTERSIL or 1-888-468-3774

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Intersil (and design) is a registered trademark of Intersil Americas Inc.

All other trademarks mentioned are the property of their respective owners.

X4323, X4325

PIN CONFIGURATION

8-Pin JEDEC SOIC

S

0

S

1

RST/RST

V

SS

1

2

3

4

8

7

6

5

V

CC

WP

SCL

SDA

8-Pin TSSOP

WP

V

CC

S

0

S

1

2

3

4

8

7

6

5

SCL

SDA

V

SS

RST/RST

PIN FUNCTION

(SOIC)

1

2

3

(TSSOP)

3

4

5

Name

S

0

S

1

RESET/

Device Select Input

Function

RESET

Reset Output.

RESET/RESET is an active LOW/HIGH, open drain output which

goes active whenever V

CC

falls below the minimum V

CC

sense level. It will remain ac-

tive until V

CC

rises above the minimum V

CC

sense level for 250ms. RESET/RESET

goes active if the Watchdog Timer is enabled and SDA remains either HIGH or LOW

longer than the selectable Watchdog time out period. A falling edge on SDA, while

SCL is HIGH, resets the Watchdog Timer. RESET/RESET goes active on power-up-

power-up and remains active for 250ms after the power supply stabilizes.

Ground

Serial Data.

SDA is a bidirectional pin used to transfer data into and out of the de-

vice. It has an open drain output and may be wire ORed with other open drain or

open collector outputs. This pin requires a pull up resistor and the input buffer is al-

ways active (not gated).

Watchdog Input.

A HIGH to LOW transition on the SDA (while SCL is HIGH) restarts

the Watchdog timer. The absence of a HIGH to LOW transition within the watchdog

time out period results in RESET/RESET going active.

Serial Clock.

The Serial Clock controls the serial bus timing for data input and output.

Write Protect.

WP HIGH used in conjunction with WPEN bit prevents writes to the

control register.

Supply Voltage

4

5

6

7

V

SS

SDA

6

7

8

1

2

SCL

WP

V

CC

2

FN8122.1

May 25, 2006

X4323, X4325

Ordering Information

PART NUMBER

RESET

(ACTIVE LOW)

X4323S8-2.7

X4323S8Z-2.7

(Note)

X4323S8I-2.7

X4323S8IZ-2.7

(Note)

X4323V8-2.7

X4323V8Z-2.7

(Note)

X4323V8I-2.7

X4323V8IZ-2.7

(Note)

X4323S8-2.7A

PART

MARKING

X4323 F

X4323 ZF

X4323 G

X4323 ZG

4323 F

4323 FZ

4323 G

4323 GZ

X4323 AN

PART NUMBER

RESET

(ACTIVE HIGH)

X4325S8-2.7

X4325S8Z-2.7

(Note)

X4325S8I-2.7

X4325S8IZ-2.7

(Note)

X4325V8-2.7

X4325V8Z-2.7

(Note)

X4325V8I-2.7

X4325V8IZ-2.7

(Note)

X4325S8-2.7A

PART

MARKING

X4325 F

X4325 ZF

X4325 G

X4325 ZG

4325 F

4325 FZ

4325 G

4325 GZ

X4325 AN

2.85 to 3.0

V

CC

RANGE V

TRIP

RANGE

TEMP.

(V)

RANGE (°C)

2.7 to 5.5

2.55 to 2.7

0 to 70

-40 to 85

0 to 70

-40 to 85

0 to 70

-40 to 85

0 to 70

-40 to 85

4.5 to 5.5

4.25 to 4.5

0 to 70

-40 to 85

0 to 70

-40 to 85

4.5 to 4.75

0 to 70

-40 to 85

PACKAGE

8 Ld SOIC (150 mil)

(Pb-free)

8 Ld SOIC (150 mil)

(Pb-free)

PKG.

DWG. #

MDP0027

8 Ld TSSOP (4.4mm) M8.173

(Pb-free)

8 Ld TSSOP (4.4mm) M8.173

(Pb-free)

8 Ld SOIC (150 mil)

(Pb-free)

8 Ld SOIC (150 mil)

(Pb-free)

MDP0027

X4323S8Z-2.7A X4323 ZAN

(Note)

X4323S8I-2.7A

X4323 AP

X4325S8Z-2.7A X4325 ZAN

(Note)

X4325S8I-2.7A

X4325 AP

X4323S8IZ-2.7A X4323 ZAP

(Note)

X4323V8-2.7A

4323 AN

X4325S8IZ-2.7A X4325 ZAP

(Note)

X4325V8-2.7A

4325 AN

8 Ld TSSOP (4.4mm) M8.173

(Pb-free)

8 Ld TSSOP (4.4mm) M8.173

(Pb-free)

8 Ld SOIC (150 mil)

(Pb-free)

8 Ld SOIC (150 mil)

(Pb-free)

MDP0027

X4323V8Z-2.7A 4323 ANZ

(Note)

X4323V8I-2.7A

4323 AP

X4325V8Z-2.7A 4325 ANZ

(Note)

X4325V8I-2.7A

4325 AP

X4323V8IZ-2.7A 4323 APZ

(Note)

X4323S8

X4323S8Z

(Note)

X4323S8I

X4323S8IZ

(Note)

X4323V8

X4323V8Z

(Note)

X4323V8I

X4323V8IZ

(Note)

X4323S8-4.5A

X4323

X4323 Z

X4323 I

X4323 ZI

4323

4323 Z

4323 I

4323 IZ

X4323 AL

X4325V8IZ-2.7A 4325 APZ

(Note)

X4325S8

X4325S8Z

(Note)

X4325S8I

X4325S8IZ

(Note)

X4325V8

X4325V8Z

(Note)

X4325V8I

X4325V8IZ

(Note)

X4325S8-4.5A

X4325

X4325 Z

X4325 I

X4325 ZI

4325

4325 Z

4325 I

4325 IZ

X4325 AL

8 Ld TSSOP (4.4mm) M8.173

(Pb-free)

8 Ld TSSOP (4.4mm) M8.173

(Pb-free)

8 Ld SOIC (150 mil)

(Pb-free)

8 Ld SOIC (150 mil)

(Pb-free)

MDP0027

X4323S8Z-4.5A X4323 ZAL

(Note)

X4323S8I-4.5A

X4323 AM

X4325S8Z-4.5A X4325 ZAL

(Note)

X4325S8I-4.5A

X4325 AM

X4323S8IZ-4.5A X4323 ZAM

(Note)

X4325S8IZ-4.5A X4325 ZAM

(Note)

3

FN8122.1

May 25, 2006

X4323, X4325

Ordering Information

(Continued)

PART NUMBER

RESET

(ACTIVE LOW)

X4323V8-4.5A

PART

MARKING

4323 AL

PART NUMBER

RESET

(ACTIVE HIGH)

X4325V8-4.5A

PART

MARKING

4325 AL

V

CC

RANGE V

TRIP

RANGE

TEMP.

(V)

RANGE (°C)

4.5 to 5.5

4.5 to 4.75

0 to 70

-40 to 85

PACKAGE

PKG.

DWG. #

8 Ld TSSOP (4.4mm) M8.173

(Pb-free)

8 Ld TSSOP (4.4mm) M8.173

(Pb-free)

X4323V8Z-4.5A 4323 ALZ

(Note)

X4323V8I-4.5A

4323 AM

X4325V8Z-4.5A 4325 ALZ

(Note)

X4325V8I-4.5A

4325 AM

X4323V8IZ-4.5A 4323 AMZ

(Note)

X4325V8IZ-4.5A 4325 AMZ

(Note)

NOTE: Intersil Pb-free plus anneal products employ special Pb-free material sets; molding compounds/die attach materials and 100% matte tin plate

termination finish, which are RoHS compliant and compatible with both SnPb and Pb-free soldering operations. Intersil Pb-free products are MSL

classified at Pb-free peak reflow temperatures that meet or exceed the Pb-free requirements of IPC/JEDEC J STD-020.

4

FN8122.1

May 25, 2006

X4323, X4325

PRINCIPLES OF OPERATION

Power-on Reset

Application of power to the X4323, X4325 activates a

Power-on Reset Circuit that pulls the RESET/RESET

pin active. This signal provides several benefits.

– It prevents the system microprocessor from starting

to operate with insufficient voltage.

– It prevents the processor from operating prior to sta-

bilization of the oscillator.

– It allows time for an FPGA to download its configura-

tion prior to initialization of the circuit.

– It prevents communication to the EEPROM, greatly

reducing the likelihood of data corruption on power-up.

When V

CC

exceeds the device V

TRIP

threshold value

for

200ms

(nominal)

the

circuit

releases

RESET/RESET allowing the system to begin operation.

LOW VOLTAGE MONITORING

During operation, the X4323, X4325 monitors the V

CC

level and asserts RESET/RESET if supply voltage

falls below a preset minimum V

TRIP

. The

RESET/RESET signal prevents the microprocessor

from operating in a power fail or brownout condition.

The RESET/RESET signal remains active until the

voltage drops below 1V. It also remains active until

V

CC

returns and exceeds V

TRIP

for 200ms.

WATCHDOG TIMER

The Watchdog Timer circuit monitors the microproces-

sor activity by monitoring the SDA and SCL pins. The

microprocessor must toggle the SDA pin HIGH to

Figure 1. Set V

TRIP

Level Sequence (V

CC

= desired V

TRIP

values WEL bit set)

LOW periodically, while SCL is HIGH (this is a start bit)

prior to the expiration of the watchdog time out period to

prevent a RESET/RESET signal. The state of two non-

volatile control bits in the Status Register determine

the watchdog timer period. The microprocessor can

change these watchdog bits, or they may be “locked”

by tying the WP pin HIGH.

EEPROM INADVERTENT WRITE PROTECTION

When RESET/RESET goes active as a result of a low

voltage condition or Watchdog Timer Time Out, any in-

progress communications are terminated. While

RESET/RESET is active, no new communications are

allowed and no nonvolatile write operation can start.

Nonvolatile writes in-progress when RESET/RESET

goes active are allowed to finish.

Additional protection mechanisms are provided with

memory Block Lock and the Write Protect (WP) pin.

These are discussed elsewhere in this document.

V

CC

THRESHOLD RESET PROCEDURE

The X4323, X4325 is shipped with a standard V

CC

threshold (V

TRIP

) voltage. This value will not change

over normal operating and storage conditions. How-

ever, in applications where the standard V

TRIP

is not

exactly right, or if higher precision is needed in the

V

TRIP

value, the X4323, X4325 threshold may be

adjusted. The procedure is described in the following

section, and uses the application of a nonvolatile con-

trol signal.

WP

V

P

= 12-15V

0 1 2 3 4 5 6 7

SCL

0 1 2 3 4 5 6 7

SDA

A0h

00h

01h

00h

5

FN8122.1

May 25, 2006

X4325V8-2.7

X4325V8-2.7 Overview

Preview

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