P4C198AL-45CM datasheet, PDF - EEWORLD Datasheet

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P4C198AL-45CM: DescriptionStandard SRAM, 16KX4, 45ns, CMOS, CDIP24, 0.300 INCH, SIDE BRAZED, CERAMIC, DIP-24; Categorystorage storage; File Size232KB，13 Pages; ManufacturerPyramid Semiconductor Corporation; Websitehttp://www.pyramidsemiconductor.com/

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P4C198AL-45CM Overview

Standard SRAM, 16KX4, 45ns, CMOS, CDIP24, 0.300 INCH, SIDE BRAZED, CERAMIC, DIP-24

P4C198AL-45CM Parametric

Parameter Name	Attribute value
Is it lead-free?	Contains lead
Is it Rohs certified?	incompatible
Maker	Pyramid Semiconductor Corporation
Parts packaging code	DIP
package instruction	DIP,
Contacts	24
Reach Compliance Code	compliant
ECCN code	3A001.A.2.C
Maximum access time	45 ns
JESD-30 code	R-CDIP-T24
JESD-609 code	e0
memory density	65536 bit
Memory IC Type	STANDARD SRAM
memory width	4
Number of functions	1
Number of terminals	24
word count	16384 words
character code	16000
Operating mode	ASYNCHRONOUS
Maximum operating temperature	125 °C
Minimum operating temperature	-55 °C
organize	16KX4
Package body material	CERAMIC, METAL-SEALED COFIRED
encapsulated code	DIP
Package shape	RECTANGULAR
Package form	IN-LINE
Parallel/Serial	PARALLEL
Peak Reflow Temperature (Celsius)	NOT SPECIFIED
Certification status	Not Qualified
Maximum seat height	5.08 mm
Maximum supply voltage (Vsup)	5.5 V
Minimum supply voltage (Vsup)	4.5 V
Nominal supply voltage (Vsup)	5 V
surface mount	NO
technology	CMOS
Temperature level	MILITARY
Terminal surface	TIN LEAD
Terminal form	THROUGH-HOLE
Terminal pitch	2.54 mm
Terminal location	DUAL
Maximum time at peak reflow temperature	NOT SPECIFIED
width	7.62 mm

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P4C198/P4C198L, P4C198A/P4C198AL

ULTRA HIGH SPEED 16K x 4

STATIC CMOS RAMS

FEATURES

Full CMOS, 6T Cell

High Speed (Equal Access and Cycle Times)

– 10/12/15/20/25 ns (Commercial)

– 12/15/20/25/35 ns (Industrial)

– 15/20/25/35/45 ns (Military)

Low Power Operation (Commercial/Military)

5V ± 10% Power Supply

Data Retention, 10

µA

Typical Current from 2.0V

P4C198L/198AL (Military)

Output Enable & Chip Enable Control Functions

– Single Chip Enable P4C198

– Dual Chip Enable P4C198A

Common Inputs and Outputs

Fully TTL Compatible Inputs and Outputs

Standard Pinout (JEDEC Approved)

– 24-Pin 300 mil DIP

– 24-Pin 300 mil SOJ

– 28-Pin 350 x 550 mil LCC

DESCRIPTION

The P4C198/L and P4C198A/L are 65,536-bit ultra high-

speed static RAMs organized as 16K x 4. Each device

features an active low Output Enable control to eliminate

data bus contention. The P4C198/L also have an active

low Chip Enable (the P4C198A/L have two Chip Enables,

both active low) for easy system expansion. The CMOS

memories require no clocks or refreshing and have equal

access and cycle times. Inputs are fully TTL-compatible.

The RAMs operate from a single 5V ± 10% tolerance

power supply. Data integrity is maintained with supply

voltages down to 2.0V. Current drain is typically 10

µA

from a 2.0V supply.

Access times as fast as 12 nanoseconds are available,

permitting greatly enhanced system operating speeds.

CMOS is used to reduce power consumption to a low 715

mW active, 193 mW standby.

The P4C198/L and P4C198A/L are available in 24-pin

300 mil DIP and SOJ, and 28-pin 350 x 550 mil LCC

packages providing excellent board level densities.

FUNCTIONAL BLOCK DIAGRAM

PIN CONFIGURATIONS

DIP (P4, C4, D4),

SOJ (J4)

P4C198 (P4C198A)

LCC (L5)

P4C198 (P4C198A)

Document #

SRAM113

REV A

Revised October 2005

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