M68AR512DL55ZB1T datasheet, PDF

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M68AR512DL55ZB1T: Description512KX16 STANDARD SRAM, 55ns, PBGA48, 8 X 10 MM, 0.75 MM PITCH, TFBGA-48; Categorystorage storage; File Size422KB，19 Pages; ManufacturerSTMicroelectronics; Websitehttp://www.st.com/

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M68AR512DL55ZB1T Overview

512KX16 STANDARD SRAM, 55ns, PBGA48, 8 X 10 MM, 0.75 MM PITCH, TFBGA-48

M68AR512DL55ZB1T Parametric

Parameter Name	Attribute value
Maker	STMicroelectronics
Parts packaging code	BGA
package instruction	TFBGA,
Contacts	48
Reach Compliance Code	unknown
ECCN code	3A991.B.2.A
Maximum access time	55 ns
JESD-30 code	R-PBGA-B48
length	10 mm
memory density	8388608 bit
Memory IC Type	STANDARD SRAM
memory width	16
Number of functions	1
Number of terminals	48
word count	524288 words
character code	512000
Operating mode	ASYNCHRONOUS
Maximum operating temperature	70 °C
Minimum operating temperature
organize	512KX16
Package body material	PLASTIC/EPOXY
encapsulated code	TFBGA
Package shape	RECTANGULAR
Package form	GRID ARRAY, THIN PROFILE, FINE PITCH
Parallel/Serial	PARALLEL
Certification status	Not Qualified
Maximum seat height	1.2 mm
Maximum supply voltage (Vsup)	1.95 V
Minimum supply voltage (Vsup)	1.65 V
Nominal supply voltage (Vsup)	1.8 V
surface mount	YES
technology	CMOS
Temperature level	COMMERCIAL
Terminal form	BALL
Terminal pitch	0.75 mm
Terminal location	BOTTOM
width	8 mm

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M68AR512D

8 Mbit (512Kb x16) 1.8V Asynchronous SRAM

FEATURES SUMMARY

SUPPLY VOLTAGE: 1.65V to 1.95V

512Kb x16 bit SRAM with OUTPUT ENABLE

EQUAL CYCLE and ACCESS TIMES: 55ns,

70ns

SINGLE BYTE READ/WRITE

LOW STANDBY CURRENT

LOW V

DATA RETENTION: 1.0V

TRI-STATE COMMON I/O

AUTOMATIC POWER DOWN

DUAL CHIP ENABLE for EASY DENSITY

EXPANSION

Figure 1. Package

BGA

)

TFBGA48 (ZB)

6 x 7mm

February 2004

1/19

M68AR512D

TABLE OF CONTENTS

FEATURES SUMMARY . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1

Figure 1. Packages . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1

SUMMARY DESCRIPTION . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3

Figure 2.

Table 1.

Figure 3.

Figure 4.

Logic Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3

Signal Names . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3

TFBGA Connections (Top view through package) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4

Block Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5

OPERATION . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6

Output Disabled . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

Read Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

Write Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

Standby/Power-Down Mode . . . . . . . . . . . . . . . . . . . . . . . . .

Table 2. Operating Modes . . . . . . . . . . . . . . . . . . . . . . . . .

......

.......

......

.....6

MAXIMUM RATING. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7

Table 3. Absolute Maximum Ratings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7

DC and AC PARAMETERS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8

Table 4. Operating and AC Measurement Conditions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8

Figure 5. AC Measurement I/O Waveform . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8

Figure 6. AC Measurement Load Circuit. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8

Table 5. Capacitance. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9

Table 6. DC Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9

Figure 7. Address Controlled, Read Mode AC Waveforms . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10

Figure 8. Chip Enable or Output Enable Controlled, Read Mode AC Waveforms . . . . . . . . . . . . . 10

Figure 9. Chip Enable or UB/LB Controlled, Standby Mode AC Waveforms . . . . . . . . . . . . . . . . . 10

Table 7. Read and Standby Mode AC Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11

Figure 10.Write Enable Controlled, Write AC Waveforms . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12

Figure 11.Chip Enable Controlled, Write AC Waveforms . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13

Figure 12.UB/LB Controlled, Write AC Waveforms . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13

Table 8. Write Mode AC Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14

Figure 13.E1 Controlled, Low V

Data Retention AC Waveforms . . . . . . . . . . . . . . . . . . . . . . . . 15

Figure 14.E2 Controlled, Low V

Data Retention AC Waveforms . . . . . . . . . . . . . . . . . . . . . . . . 15

Table 9. Low V

Data Retention Characteristics. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15

)

PACKAGE MECHANICAL . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16

Figure 15.TFBGA48 6x7mm - 6x8 ball array, 0.75 mm pitch, Bottom View Package Outline. . . . . 16

Table 10. TFBGA48 6x7mm - 6x8 ball array, 0.75 mm pitch, Package Mechanical Data. . . . . . . . 16

PART NUMBERING . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17

Table 11. Ordering Information Scheme . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17

2/19

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