The AD8522 is a complete dual 12-bit, single-supply, voltage
output DAC in a 14-pin DIP, or SO-14 surface mount package.
Fabricated in a CBCMOS process, features include a serial digi-
tal interface, onboard reference, and buffered voltage output.
Ideal for +5 V-only systems, this monolithic device offers low
cost and ease of use, and requires no external components to
realize the full performance of the device.
The serial digital interface allows interfacing directly to numer-
ous microcontroller ports, with a simple high speed, three-wire
data, clock, and load strobe format. The 16-bit serial word con-
tains the 12-bit data word and DAC select address, which is de-
coded internally or can be decoded externally using
LDA, LDB
0.6
0.4
LINEARITY ERROR – LSB
inputs. A serial data output allows the user to easily daisy-chain
multiple devices in conjunction with a chip select input. A reset
RS
input sets the outputs to zero scale or midscale, as deter-
mined by the input MSB.
The output 4.095 V full scale is laser trimmed to maintain accu-
racy over the operating temperature range of the device, and
gives the user an easy-to-use one-millivolt-per-bit resolution. A
2.5 V reference output is also available externally for other data
acquisition circuitry, and for ratiometric applications. The out-
put buffers are capable of driving
±
5 mA.
The AD8522 is available in the 14-pin plastic DIP and low pro-
file 1.5 mm SOIC-14 packages.
PACKAGE TYPES AVAILABLE
V
DD
= +4.5V
T
A
= –55°C, +25°C, +85°C, +125°C
+25°C
–55°C
0.2
0
–0.2
–0.4
–0.6
–0.8
–1.0
0
+85°C
PDIP-14
SO-14
+125°C
1024
2048
3072
DIGITAL INPUT CODE – Decimal
4096
Figure 1. Linearity Error vs. Digital Code & Temperature
REV. A
Information furnished by Analog Devices is believed to be accurate and
reliable. However, no responsibility is assumed by Analog Devices for its
use, nor for any infringements of patents or other rights of third parties
which may result from its use. No license is granted by implication or
otherwise under any patent or patent rights of Analog Devices.
One Technology Way, P.O. Box 9106, Norwood. MA 02062-9106, U.S.A.
Tel: 617/329-4700
Fax: 617/326-8703
AD8522–SPECIFICATIONS
V
(@
ELECTRICAL CHARACTERISTICS
Parameter
STATIC PERFORMANCE
Resolution
1
Relative Accuracy
Differential Nonlinearity
Zero-Scale Error
Full-Scale Voltage
2
Full-Scale Tempco
2, 3
MATCHING PERFORMANCE
Linearity Matching Error
ANALOG OUTPUT
Output Current
Load Regulation at Half-Scale
Capacitive Load
3
REFERENCE OUTPUT
Output Voltage
Output Source Current
4
Line Rejection
Load Regulation
LOGIC INPUTS & OUTPUTS
Logic Input Low Voltage
Logic Input High Voltage
Input Leakage Current
Input Capacitance
3
Logic Output Voltage Low
Logic Output Voltage High
TIMING SPECIFICATIONS
3, 5
Clock Width High
Clock Width Low
Load Pulse Width
Data Setup
Data Hold
Clear Pulse Width
Load Setup
Load Hold
Select
Deselect
Clock to SDO Propagation Delay
AC CHARACTERISTICS
3, 5
Voltage Output Settling Time
6
Crosstalk
DAC Glitch
Digital Feedthrough
SUPPLY CHARACTERISTICS
Positive Supply Current
Power Dissipation
7
Power Supply Sensitivity
Symbol
N
INL
DNL
V
ZSE
V
FS
TCV
FS
∆V
FS
A/B
I
OUT
LD
REG
C
L
V
REF
I
REF
LN
REJ
LD
REG
V
IL
V
IH
I
IL
C
IL
V
OL
V
OH
t
CH
t
CL
t
LDW
t
DS
t
DH
t
CLRW
t
LD1
t
LD2
t
CSS
t
CSH
t
PD
t
S
C
T
Q
D
FT
= +5.0 V
otherwise noted)
DD
10%, R
L
= No Load, –40 C
≤
T
A
≤
+85 C, both DACs tested, unless
Condition
Min
12
-1.5
-1
4.079
Typ
Max
Units
Bits
LSB
LSB
mV
Volts
ppm/°C
LSB
Monotonic
Data = 000
H
Data = FFF
H
±
0.5
±
0.5
+0.5
4.095
±
15
±
1
+1.5
+1
+3
4.111
Data = 800
H
,
∆V
OUT
≤
3 LSB
R
L
= 402
Ω
to
∞,
Data = 800
H
No Oscillation
2.484
1
500
2.500
0.025
0.025
±
5
3
mA
LSB
pF
V
mA
%/V
%/mA
V
V
µA
pF
V
V
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
µs
dB
nV s
nV s
∆V
REF
< 18 mV
I
REF
= 0 to 5 mA, Data = 800
H
2.516
5
0.08
0.1
0.8
2.4
I
OL
= 1.6 mA
I
OH
= 400
µA
10
10
0.4
3.5
35
35
25
10
20
20
10
10
30
30
20
To
±
1 LSB of Final Value
Signal Measured at DAC Output,
While Changing Opposite
LDA/B
Half-Scale Transition
Signal Measured at DAC Output,
While Changing Data Without
LDA/B
V
DD
= 5.5 V, V
IH
= 2.4 V or V
IL
= 0.8 V
V
DD
= 5 V, V
IL
= 0 V
V
DD
= 5 V, V
IH
= 2.4 V or V
IL
= 0.8 V
V
DD
= 5 V, V
IL
= 0 V
∆V
DD
=
±
5%
45
16
38
13
2
3
1
15
5
0.002
80
I
DD
P
DISS
PSS
5
2
25
10
0.004
mA
mA
mW
mW
%/%
NOTES
1
1 LSB = 1 mV for 0 V to +4.095 V output range.
2
Includes internal voltage reference error.
3
These parameters are guaranteed by design and not subject to production testing.
4
Very little sink current is available at the V
REF
pin. Use external buffer if setting up a virtual ground.
5
All input control signals are specified with t
r
= t
f
= 5 ns (10% to 90% of +5 V) and timed from a voltage level of 1.6 V.
6
The settling time specification does not apply for negative going transitions within the last 6 LSBs of ground. Some devices exhibit double the typical settling time in this 6 LSB region.
7
Power Dissipation is calculated I
DD
×
5 V.
Specifications subject to change without notice.
–2–
REV. A
AD8522
SDI
Sf/Hd
B
A
NC
DB11
DB10
DB4
DB3
DB2
DB1
DB0
CLK
t
CSS
CS
t
CSH
t
LD2
t
LDW
t
PD
t
LD1
LD
SDO
SDI
t
CH
CLK
t
DS
t
CL
t
DH
t
LD2
t
LDW
t
CLRW
LD
RS
FS
V
OUT
ZS
t
S
t
S
±1
LSB
ERROR BAND
Figure 2. Timing Diagram
SERIAL INPUT REGISTER DATA FORMAT
Last
D0
DB0
D1
DB1
D2
DB2
D3
DB3
D4
DB4
D5
DB5
D6
DB6
D7
DB7
D8
DB8
D9
DB9
D10
D11
D12
D13
A
D14
B
First
D15
Sf/Hd
DB10 DB11 NC
Table I. Truth Table
Data Word
Sf/Hd
B
A
X
X
X
X
L
L
L
H
H
H
H
Ext Pins
LDA
↓
↓
H
H
X
↓
H
↓
H
↓
H
LDB
↓
H
↓
H
X
↓
H
↓
H
↓
H
DAC Register
Loads DACA + DACB with Data from SR
Loads DACA with Data from SR
Loads DACB with Data from SR
No Load
No Load
Loads DACB with Data from SR, See Note 1 Below
No Load
Loads DACA with Data from SR, See Note 1 Below
No Load
Loads DACA + DACB with Data from SR, See 1 Note Below
No Load
Hardware Load:
L
X
L
X
L
X
L
X
Software Decode Load:
H
L
H
H
H
H
H
L
H
L
H
H
H
H
NOTES
1
In software mode
LDA
and
LDB
perform the same function. They can be tied together or the unused pin should be tied high.
2
External Pins
LDA
and
LDB
should always be high when shifting Data into the shift register.
3
↓
symbol denotes negative transition.
1.6mA
SDO
1.6 VOLT
200µA
Figure 3. AC Timing SDO Pin Load Circuit
REV. A
–3–
AD8522
PIN DESCRIPTION
Pin
SDI
CLK
CS
LDA/B
Function
Serial Data Input, input data loads directly into the shift register.
Clock input, positive edge clocks data into shift register.
Chip Select, active low input. Prevents shift register loading when high. Does not affect
LDA
and
LDB
operation.
Load DAC register strobes, active low. Transfers shift register data to DAC register. See truth table for operation.
Software decode feature only requires one
LD
strobe. Tie
LDA
and
LDB
together or use one of them with the
other pin tied high.
Serial Data Output. Output of shift register, always active.
Resets DAC registers to condition determined by MSB pin. Active low input.
Digital input: High presets DAC registers to half scale (800
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