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IDT7015L20GB

Description
Dual-Port SRAM, 8KX9, 20ns, CMOS, CPGA68, CERAMIC, PGA-68
Categorystorage    storage   
File Size168KB,20 Pages
ManufacturerIDT (Integrated Device Technology)
Download Datasheet Parametric View All

IDT7015L20GB Overview

Dual-Port SRAM, 8KX9, 20ns, CMOS, CPGA68, CERAMIC, PGA-68

IDT7015L20GB Parametric

Parameter NameAttribute value
Is it lead-free?Contains lead
Is it Rohs certified?incompatible
MakerIDT (Integrated Device Technology)
Parts packaging codePGA
package instructionCERAMIC, PGA-68
Contacts68
Reach Compliance Codenot_compliant
ECCN code3A001.A.2.C
Maximum access time20 ns
Other featuresINTERRUPT FLAG; SEMAPHORE; AUTOMATIC POWER-DOWN
I/O typeCOMMON
JESD-30 codeS-CPGA-P68
JESD-609 codee0
length29.464 mm
memory density73728 bit
Memory IC TypeDUAL-PORT SRAM
memory width9
Number of functions1
Number of ports2
Number of terminals68
word count8192 words
character code8000
Operating modeASYNCHRONOUS
Maximum operating temperature125 °C
Minimum operating temperature-55 °C
organize8KX9
Output characteristics3-STATE
ExportableYES
Package body materialCERAMIC, METAL-SEALED COFIRED
encapsulated codePGA
Encapsulate equivalent codePGA68,11X11
Package shapeSQUARE
Package formGRID ARRAY
Parallel/SerialPARALLEL
Peak Reflow Temperature (Celsius)225
power supply5 V
Certification statusNot Qualified
Filter levelMIL-PRF-38535
Maximum seat height5.207 mm
Maximum standby current0.01 A
Minimum standby current4.5 V
Maximum slew rate0.31 mA
Maximum supply voltage (Vsup)5.5 V
Minimum supply voltage (Vsup)4.5 V
Nominal supply voltage (Vsup)5 V
surface mountNO
technologyCMOS
Temperature levelMILITARY
Terminal surfaceTin/Lead (Sn/Pb)
Terminal formPIN/PEG
Terminal pitch2.54 mm
Terminal locationPERPENDICULAR
Maximum time at peak reflow temperature30
width29.464 mm
HIGH-SPEED
8K x 9 DUAL-PORT
STATIC RAM
FEATURES:
x
x
x
IDT7015S/L
x
x
True Dual-Ported memory cells which allow simultaneous
reads of the same memory location
High-speed access
– Military: 20/25/35ns (max.)
– Commercial: 12/15/17/20/25/35ns (max.)
Low-power operation
– IDT7015S
Active: 750mW (typ.)
Standby: 5mW (typ.)
– IDT7015L
Active: 750mW (typ.)
Standby: 1mW (typ.)
IDT7015 easily expands data bus width to 18 bits or more
using the Master/Slave select when cascading more than
one device
x
x
x
x
x
x
x
M/S = V
IH
for
BUSY
output flag on Master
M/S = V
IL
for
BUSY
input on Slave
Busy and Interrupt Flag
On-chip port arbitration logic
Full on-chip hardware support of semaphore signaling
between ports
Fully asynchronous operation from either port
TTL-compatible, single 5V (±10%) power supply
Available in ceramic 68-pin PGA, 68-pin PLCC, and an 80-
pin TQFP
Industrial temperature range (–40°C to +85°C) is available
for selected speeds
Functional Block Diagram
OE
L
CE
L
R/W
L
OE
R
CE
R
R/W
R
I/O
0L
- I/O
8L
I/O
Control
BUSY
L
A
12L
A
0L
(1,2)
I/O
Control
I/O
0R
-I/O
8R
BUSY
R
A
12R
A
0R
(1,2)
Address
Decoder
13
MEMORY
ARRAY
13
Address
Decoder
CE
L
OE
L
R/W
L
ARBITRATION
INTERRUPT
SEMAPHORE
LOGIC
CE
R
OE
R
R/W
R
SEM
L
(2)
INT
L
NOTES:
1. In MASTER mode:
BUSY
is an output and is a push-pull driver
In SLAVE mode:
BUSY
is input.
2.
BUSY
outputs and
INT
outputs are non-tri-stated push-pull drivers.
M/S
2954 drw 01
SEM
R
(2)
INT
R
MAY 2000
1
©2000 Integrated Device Technology, Inc.
DSC 2954/5
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