NAND02GW4B2AZB1F datasheet, PDF

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NAND02GW4B2AZB1F: Description128MX16 FLASH 3V PROM, 25000ns, PBGA63, 9.50 X 12 MM, 1.20 MM HEIGHT, 0.80 MM PITCH, LEAD FREE, TFBGA-63; Categorystorage storage; File Size632KB，64 Pages; ManufacturerSTMicroelectronics; Websitehttp://www.st.com/; Environmental Compliance

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NAND02GW4B2AZB1F Overview

128MX16 FLASH 3V PROM, 25000ns, PBGA63, 9.50 X 12 MM, 1.20 MM HEIGHT, 0.80 MM PITCH, LEAD FREE, TFBGA-63

NAND02GW4B2AZB1F Parametric

Parameter Name	Attribute value
Is it Rohs certified?	conform to
Maker	STMicroelectronics
Parts packaging code	BGA
package instruction	TFBGA, BGA63,10X12,32
Contacts	63
Reach Compliance Code	unknown
ECCN code	3A991.B.1.A
Maximum access time	25000 ns
command user interface	YES
Data polling	NO
JESD-30 code	R-PBGA-B63
JESD-609 code	e1
length	12 mm
memory density	2147483648 bit
Memory IC Type	FLASH
memory width	16
Number of functions	1
Number of departments/size	2K
Number of terminals	63
word count	134217728 words
character code	128000000
Operating mode	ASYNCHRONOUS
Maximum operating temperature	70 °C
Minimum operating temperature
organize	128MX16
Package body material	PLASTIC/EPOXY
encapsulated code	TFBGA
Encapsulate equivalent code	BGA63,10X12,32
Package shape	RECTANGULAR
Package form	GRID ARRAY, THIN PROFILE, FINE PITCH
page size	1K words
Parallel/Serial	PARALLEL
Peak Reflow Temperature (Celsius)	260
power supply	3/3.3 V
Programming voltage	3 V
Certification status	Not Qualified
ready/busy	YES
Maximum seat height	1.2 mm
Department size	64K
Maximum standby current	0.00005 A
Maximum slew rate	0.03 mA
Maximum supply voltage (Vsup)	3.6 V
Minimum supply voltage (Vsup)	2.7 V
Nominal supply voltage (Vsup)	3 V
surface mount	YES
technology	CMOS
Temperature level	COMMERCIAL
Terminal surface	Tin/Silver/Copper (Sn/Ag/Cu)
Terminal form	BALL
Terminal pitch	0.8 mm
Terminal location	BOTTOM
Maximum time at peak reflow temperature	30
switch bit	NO
width	9.5 mm

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NAND01G-B

NAND02G-B

1 Gbit, 2 Gbit,

2112 Byte/1056 Word Page, 1.8V/3V, NAND Flash Memory

Feature summary

●

High Density NAND Flash memories

–

Up to 2 Gbit memory array

Up to 64Mbit spare area

Cost effective solutions for mass

storage applications

x8 or x16 bus width

Multiplexed Address/ Data

Pinout compatibility for all densities

FBGA

●

NAND interface

–

TSOP48 12 x 20mm

●

Supply voltage

–

1.8V device: V

= 1.7 to 1.95V

3.0V device: V

= 2.7 to 3.6V

x8 device: (2048 + 64 spare) Bytes

x16 device: (1024 + 32 spare) Words

x8 device: (128K + 4K spare) Bytes

x16 device: (64K + 2K spare) Words

Random access: 25µs (max)

Sequential access: 50ns (min)

Page program time: 300µs (typ)

■

●

Page size

–

VFBGA63 9.5 x 12 x 1mm

TFBGA63 9.5 x 12 x 1.2mm

●

Block size

–

Serial Number option

Data protection

–

Hardware and Software Block Locking

Hardware Program/Erase locked during

Power transitions

100,000 Program/Erase cycles

10 years Data Retention

●

Page Read/Program

–

●

Data integrity

–

●

Copy Back Program mode

–

Fast page copy without external

buffering

Internal Cache Register to improve the

program and read throughputs

Block erase time: 2ms (typ)

ECOPACK

packages

Development tools

–

Error Correction Code software and

hardware models

Bad Blocks Management and Wear

Leveling algorithms

File System OS Native reference

software

Hardware simulation models

●

Cache Program and Cache Read modes

–

●

Fast Block Erase

–

Status Register

Electronic Signature

Chip Enable ‘don’t care’

–

for simple interface with microcontroller

●

February 2006

Rev 4.0

1/64

www.st.com

NAND01G-B, NAND02G-B

Contents

Summary description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8

Memory array organization . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15

2.1

Bad blocks . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15

Signal descriptions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17

3.1

3.2

3.3

3.4

3.5

3.6

3.7

3.8

3.9

3.10

3.11

3.12

Inputs/Outputs (I/O0-I/O7) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17

Inputs/Outputs (I/O8-I/O15) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17

Address Latch Enable (AL) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17

Command Latch Enable (CL) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17

Chip Enable (E) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17

Read Enable (R) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17

Power-Up Read Enable, Lock/Unlock Enable (PRL) . . . . . . . . . . . . . . . . 18

Write Enable (W) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18

Write Protect (WP) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18

Ready/Busy (RB) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18

Supply Voltage . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18

Ground . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19

Bus operations . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19

4.1

4.2

4.3

4.4

4.5

4.6

Command Input . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19

Address Input . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19

Data Input . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19

Data Output . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20

Write Protect . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20

Standby . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20

Command Set . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22

Device operations . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23

6.1

Read Memory Array . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23

6.1.1

Random Read . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23

3/64

Contents

6.1.2

NAND01G-B, NAND02G-B

Page Read . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23

6.2

6.3

Cache Read . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26

Page Program . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27

6.3.1

6.3.2

Sequential Input . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27

Random Data Input . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27

6.4

6.5

6.6

6.7

6.8

Copy Back Program . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29

Cache Program . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 31

Block Erase . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 32

Reset . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 32

Read Status Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 33

6.8.1

6.8.2

6.8.3

6.8.4

6.8.5

6.8.6

Write Protection Bit (SR7) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 33

P/E/R Controller and Cache Ready/Busy Bit (SR6) . . . . . . . . . . . . . . . 33

P/E/R Controller Bit (SR5) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 33

Cache Program Error Bit (SR1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 34

Error Bit (SR0) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 34

SR4, SR3 and SR2 are Reserved . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 34

6.9

Read Electronic Signature . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 35

Data protection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 36

7.1

7.2

7.3

7.4

Blocks Lock . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 36

Blocks Unlock . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 36

Blocks Lock-Down . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 37

Block Lock Status . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 37

Software algorithms . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 40

8.1

8.2

8.3

8.4

8.5

8.6

Bad Block Management . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 40

Block Replacement . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 40

Garbage Collection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 42

Wear-leveling algorithm . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 42

Error Correction Code . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 42

Hardware Simulation models . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 43

8.6.1

8.6.2

Behavioral simulation models . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 43

IBIS simulations models . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 43

Program and Erase Times and Endurance cycles . . . . . . . . . . . . . . . . 44

4/64

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