LPC2470
Flashless 16-bit/32-bit microcontroller; Ethernet, CAN, LCD,
USB 2.0 device/host/OTG, external memory interface
Rev. 3 — 14 February 2011
Product data sheet
1. General description
NXP Semiconductors designed the LPC2470 microcontroller, powered by the
ARM7TDMI-S core, to be a highly integrated microcontroller for a wide range of
applications that require advanced communications and high quality graphic displays. The
LPC2470 microcontroller is flashless. The LPC2470, with real-time debug interfaces that
include both JTAG and embedded trace, can execute both 32-bit ARM and 16-bit Thumb
instructions.
The LPC2470 microcontroller incorporates an LCD controller, a 10/100 Ethernet Media
Access Controller (MAC), a USB full-speed device/host/OTG controller with 4 kB of
endpoint RAM, four UARTs, two Controller Area Network (CAN) channels, an SPI
interface, two Synchronous Serial Ports (SSP), three I
2
C interfaces, and an I
2
S interface.
Supporting this collection of serial communications interfaces are the following feature
components; an on-chip 4 MHz internal oscillator, 98 kB of total RAM consisting of 64 kB
of local SRAM, 16 kB SRAM for Ethernet, 16 kB SRAM for general purpose DMA, 2 kB of
battery powered SRAM, and an External Memory Controller (EMC). These features make
this device optimally suited for portable electronics and Point-of-Sale (POS) applications.
Complementing the many serial communication controllers, versatile clocking capabilities,
and memory features are various 32-bit timers, a 10-bit ADC, 10-bit DAC, two PWM units,
and up to 160 fast GPIO lines. The LPC2470 connects 64 of the GPIO pins to the
hardware based Vector Interrupt Controller (VIC) that means these external inputs can
generate edge-triggered interrupts. All of these features make the LPC2470 particularly
suitable for industrial control and medical systems.
2. Features and benefits
ARM7TDMI-S processor, running at up to 72 MHz.
98 kB on-chip SRAM includes:
64 kB of SRAM on the ARM local bus for high performance CPU access.
16 kB SRAM for Ethernet interface. Can also be used as general purpose SRAM.
16 kB SRAM for general purpose DMA use also accessible by the USB.
2 kB SRAM data storage powered from the Real-Time Clock (RTC) power domain.
LCD controller, supporting both Super-Twisted Nematic (STN) and Thin-Film
Transistors (TFT) displays.
Dedicated DMA controller.
Selectable display resolution (up to 1024
×
768 pixels).
Supports up to 24-bit true-color mode.
Dual Advanced High-performance Bus (AHB) system allows simultaneous Ethernet
DMA, and USB DMA with no contention.
NXP Semiconductors
LPC2470
Flashless 16-bit/32-bit microcontroller
EMC provides support for asynchronous static memory devices such as RAM, ROM
and flash, as well as dynamic memories such as single data rate SDRAM.
Advanced Vectored Interrupt Controller (VIC), supporting up to 32 vectored interrupts.
General Purpose DMA controller (GPDMA) on AHB that can be used with the SSP,
I
2
S-bus, and Secure Digital/MultiMediaCard (SD/MMC) interface as well as for
memory-to-memory transfers.
Serial Interfaces:
Ethernet MAC with MII/RMII interface and associated DMA controller. These
functions reside on an independent AHB.
USB 2.0 full-speed dual port device/host/OTG controller with on-chip PHY and
associated DMA controller.
Four UARTs with fractional baud rate generation, one with modem control I/O, one
with IrDA support, all with FIFO.
CAN controller with two channels.
SPI controller.
Two SSP controllers, with FIFO and multi-protocol capabilities. One is an alternate
for the SPI port, sharing its interrupt. SSPs can be used with the GPDMA controller.
Three I
2
C-bus interfaces (one with open-drain and two with standard port pins).
I
2
S (Inter-IC Sound) interface for digital audio input or output. It can be used with
the GPDMA.
Other peripherals:
SD/MMC memory card interface.
160 General purpose I/O pins with configurable pull-up/down resistors.
10-bit ADC with input multiplexing among 8 pins.
10-bit DAC.
Four general purpose timers/counters with 8 capture inputs and 10 compare
outputs. Each timer block has an external count input.
Two PWM/timer blocks with support for three-phase motor control. Each PWM has
an external count inputs.
RTC with separate power domain. Clock source can be the RTC oscillator or the
APB clock.
2 kB SRAM powered from the RTC power pin, allowing data to be stored when the
rest of the chip is powered off.
WatchDog Timer (WDT). The WDT can be clocked from the internal RC oscillator,
the RTC oscillator, or the APB clock.
Single 3.3 V power supply (3.0 V to 3.6 V).
4 MHz internal RC oscillator trimmed to 1 % accuracy that can optionally be used as
the system clock.
Four reduced power modes: idle, sleep, power-down, and deep power-down.
Four external interrupt inputs configurable as edge/level sensitive. All pins on port 0
and port 2 can be used as edge sensitive interrupt sources.
Processor wake-up from Power-down mode via any interrupt able to operate during
Power-down mode (includes external interrupts, RTC interrupt, USB activity, Ethernet
wake-up interrupt, CAN bus activity, port 0/2 pin interrupt).
Two independent power domains allow fine tuning of power consumption based on
needed features.
LPC2470
All information provided in this document is subject to legal disclaimers.
© NXP B.V. 2011. All rights reserved.
Product data sheet
Rev. 3 — 14 February 2011
2 of 89
NXP Semiconductors
LPC2470
Flashless 16-bit/32-bit microcontroller
Each peripheral has its own clock divider for further power saving. These dividers help
reduce active power by 20 % to 30 %.
Brownout detect with separate thresholds for interrupt and forced reset.
On-chip power-on reset.
On-chip crystal oscillator with an operating range of 1 MHz to 25 MHz.
On-chip PLL allows CPU operation up to the maximum CPU rate without the need for
a high frequency crystal. May be run from the main oscillator, the internal RC oscillator,
or the RTC oscillator.
Boundary scan for simplified board testing.
Versatile pin function selections allow more possibilities for using on-chip peripheral
functions.
Standard ARM test/debug interface for compatibility with existing tools.
Emulation trace module supports real-time trace.
3. Applications
Industrial control
Medical systems
Portable electronics
Point-of-Sale (POS) equipment
4. Ordering information
Table 1.
Ordering information
Package
Name
LPC2470FBD208 LQFP208
Description
plastic low profile quad flat package; 208 leads; body 28
×
28
×
1.4 mm
Version
SOT459-1
SOT950-1
Type number
LPC2470FET208 TFBGA208 plastic thin fine-pitch ball grid array package; 208 balls;
body 15
×
15
×
0.7 mm
4.1 Ordering options
Table 2.
Ordering options
Flash
(kB)
Local bus
SRAM (kB)
Ethernet buffer
External bus Ethernet USB
OTG/
OHCI/
device
+ 4 kB
FIFO
SD/
GP
MMC DMA
CAN channels
ADC channels
yes
yes
yes
yes
8
8
DAC channels
1
1
−40 °C
to
+85
°C
−40 °C
to
+85
°C
Temp range
Type number
GP/USB
LPC2470FBD208 n/a
LPC2470FET208
n/a
64 16 16 2
64 16 16 2
98 Full 32-bit
98 Full 32-bit
Total
RTC
MII/RMII
MII/RMII
yes
yes
2
2
LPC2470
All information provided in this document is subject to legal disclaimers.
© NXP B.V. 2011. All rights reserved.
Product data sheet
Rev. 3 — 14 February 2011
3 of 89
NXP Semiconductors
LPC2470
Flashless 16-bit/32-bit microcontroller
5. Block diagram
XTAL1
V
DD(3V3)
XTAL2
V
DDA
TMS TDI
trace signals
TRST
TCK TDO
EXTIN0 DBGEN
RESET
VREF
V
SSA
, V
SSCORE
, V
SSIO
V
DD(DCDC)(3V3)
TEST/DEBUG
INTERFACE
EMULATION
TRACE MODULE
P0, P1, P2,
P3, P4
LPC2470
64 kB
SRAM
PLL
system
clock
SYSTEM
FUNCTIONS
INTERNAL RC
OSCILLATOR
HIGH-SPEED
GPIO
160 PINS
TOTAL
INTERNAL
SRAM
CONTROLLER
ARM7TDMI-S
VIC
16 kB
SRAM
EXTERNAL
MEMORY
CONTROLLER
AHB1
D[31:0]
A[23:0]
control lines
AHB2
AHB
BRIDGE
AHB
BRIDGE
USB DEVICE/
HOST/OTG WITH
4 kB RAM AND DMA
GP DMA
CONTROLLER
LCD INTERFACE
WITH DMA
8
×
LCD control
LCDVD[23:0]
LCDCLKIN
V
BUS
port1
port2
MII/RMII
ETHERNET
MAC WITH
DMA
16 kB
SRAM
MASTER AHB TO SLAVE
PORT AHB BRIDGE PORT
AHB TO
APB BRIDGE
EINT3 to EINT0
P0, P2
2
×
CAP0/CAP1/
CAP2/CAP3
4
×
MAT2/MAT3,
2
×
MAT0,
3
×
MAT1
6
×
PWM0/PWM1
1
×
PCAP0,
2
×
PCAP1
P0, P1
EXTERNAL INTERRUPTS
CAPTURE/COMPARE
TIMER0/TIMER1/
TIMER2/TIMER3
I
2
S INTERFACE
PWM0, PWM1
SPI, SSP0 INTERFACE
LEGACY GPI/O
64 PINS TOTAL
SSP1 INTERFACE
3
×
I2SRX
3
×
I2STX
SCK, SCK0
MOSI, MOSI0
MISO, MISO0
SSEL, SSEL0
SCK1
MOSI1
MISO1
SSEL1
MCICLK, MCIPWR
MCICMD,
MCIDAT[3:0]
TXD0, TXD2, TXD3
RXD0, RXD2, RXD3
TXD1, DTR1, RTS1
RXD1, DSR1, CTS1,
DCD1, RI1
RD1, RD2
TD1, TD2
SCL0, SCL1, SCL2
SDA0, SDA1, SDA2
8
×
AD0
A/D CONVERTER
SD/MMC CARD
INTERFACE
AOUT
VBAT
power domain 2
RTCX1
RTCX2
ALARM
D/A CONVERTER
2 kB BATTERY RAM
UART0, UART2, UART3
RTC
OSCILLATOR
REAL-
TIME
CLOCK
UART1
CAN1, CAN2
WATCHDOG TIMER
SYSTEM CONTROL
I
2
C0, I
2
C1, I
2
C2
002aad317
Fig 1.
LPC2470 block diagram
LPC2470
All information provided in this document is subject to legal disclaimers.
© NXP B.V. 2011. All rights reserved.
Product data sheet
Rev. 3 — 14 February 2011
4 of 89
NXP Semiconductors
LPC2470
Flashless 16-bit/32-bit microcontroller
6. Pinning information
6.1 Pinning
208
157
156
105
104
4
3
5
6
7
8
9
53
002aad318
1
LPC2470FBD208
52
Fig 2.
LPC2470 pinning LQFP208 package
ball A1
index area
1
A
B
C
D
E
F
G
H
J
K
L
M
N
P
R
T
U
2
10 12 14 16
11 13 15 17
LPC2470FET208
002aad319
Transparent top view
Fig 3.
Table 3.
Row A
1
5
P3[27]/D27/
CAP1[0]/PWM1[4]
P1[4]/ENET_TX_EN
2
6
Pin allocation table
LPC2470 pinning TFBGA208 package
Pin Symbol
Pin Symbol
V
SSIO
P1[9]/ENET_RXD0
Pin Symbol
3
7
P1[0]/ENET_TXD0
P1[14]/ENET_RX_ER
Pin Symbol
4
8
P4[31]/CS1
P1[15]/
ENET_REF_CLK/
ENET_RX_CLK
V
SSIO
9
P1[17]/ENET_MDIO
10
P1[3]/ENET_TXD3/
MCICMD/PWM0[2]
11
P4[15]/A15
12
LPC2470
All information provided in this document is subject to legal disclaimers.
© NXP B.V. 2011. All rights reserved.
Product data sheet
Rev. 3 — 14 February 2011
5 of 89
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