TS87C58X2-VCBB datasheet, PDF - EEWORLD Datasheet

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TS87C58X2-VCBB: DescriptionMicrocontroller, 8-Bit, OTPROM, 8051 CPU, 40MHz, CMOS, PQCC44, PLASTIC, LCC-44; CategoryThe embedded processor and controller Microcontrollers and processors; File Size597KB，58 Pages; ManufacturerAtmel (Microchip)

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TS87C58X2-VCBB Overview

Microcontroller, 8-Bit, OTPROM, 8051 CPU, 40MHz, CMOS, PQCC44, PLASTIC, LCC-44

TS87C58X2-VCBB Parametric

Parameter Name	Attribute value
Is it Rohs certified?	incompatible
Maker	Atmel (Microchip)
Parts packaging code	LCC
package instruction	QCCJ, LDCC44,.7SQ
Contacts	44
Reach Compliance Code	compliant
ECCN code	3A991.A.2
Has ADC	NO
Address bus width	16
bit size	8
CPU series	8051
maximum clock frequency	40 MHz
DAC channel	NO
DMA channel	NO
External data bus width	8
JESD-30 code	S-PQCC-J44
JESD-609 code	e0
length	16.5862 mm
Humidity sensitivity level	2
Number of I/O lines	32
Number of terminals	44
Maximum operating temperature	70 °C
Minimum operating temperature
PWM channel	NO
Package body material	PLASTIC/EPOXY
encapsulated code	QCCJ
Encapsulate equivalent code	LDCC44,.7SQ
Package shape	SQUARE
Package form	CHIP CARRIER
Peak Reflow Temperature (Celsius)	225
power supply	5 V
Certification status	Not Qualified
RAM (bytes)	256
rom(word)	32768
ROM programmability	OTPROM
Maximum seat height	4.57 mm
speed	40 MHz
Maximum slew rate	27 mA
Maximum supply voltage	5.5 V
Minimum supply voltage	4.5 V
Nominal supply voltage	5 V
surface mount	YES
technology	CMOS
Temperature level	COMMERCIAL
Terminal surface	Tin/Lead (Sn/Pb)
Terminal form	J BEND
Terminal pitch	1.27 mm
Terminal location	QUAD
Maximum time at peak reflow temperature	30
width	16.5862 mm
uPs/uCs/peripheral integrated circuit type	MICROCONTROLLER

TS87C58X2-VCBB Preview

TS80C54X2/C58X2

TS87C54X2/C58X2

8-bit CMOS Microcontroller 16/32 Kbytes ROM/OTP

1. Description

TS80C54/58X2 is high performance CMOS ROM, OTP

and EPROM versions of the 80C51 CMOS single chip

8-bit microcontroller.

The TS80C54/58X2 retains all features of the Atmel

Wireless & Microcontrollers 80C51 with extended

ROM/EPROM capacity (16/32 Kbytes), 256 bytes of

internal RAM, a 6-source , 4-level interrupt system, an

on-chip oscilator and three timer/counters.

In addition, the TS80C54/58X2 has a Hardware

Watchdog Timer, a more versatile serial channel that

facilitates multiprocessor communication (EUART) and

a X2 speed improvement mechanism.

The fully static design of the TS80C54/58X2 allows to

reduce system power consumption by bringing the clock

frequency down to any value, even DC, without loss of

data.

The TS80C54/58X2 has 2 software-selectable modes of

reduced activity for further reduction in power

consumption. In the idle mode the CPU is frozen while

the timers, the serial port and the interrupt system are still

operating. In the power-down mode the RAM is saved

and all other functions are inoperative.

2. Features

80C52 Compatible

•

8051 pin and instruction compatible

•

Four 8-bit I/O ports

•

Three 16-bit timer/counters

•

256 bytes scratchpad RAM

Interrupt Structure with

•

6 Interrupt sources

•

4 level priority interrupt system

Full duplex Enhanced UART

•

Framing error detection

•

Automatic address recognition

High-Speed Architecture

•

40 MHz @ 5V, 30MHz @ 3V

•

X2 Speed Improvement capability (6 clocks/

machine cycle)

30 MHz @ 5V, 20 MHz @ 3V (Equivalent to

60 MHz @ 5V, 40 MHz @ 3V)

Low EMI (inhibit ALE)

Power Control modes

•

Idle mode

•

Power-down mode

•

Power-off Flag

Dual Data Pointer

On-chip ROM/EPROM (16K-bytes, 32K-bytes)

Programmable Clock Out and Up/Down Timer/

Counter 2

Hardware Watchdog Timer (One-time enabled with

Reset-Out)

Asynchronous port reset

Once mode (On-chip Emulation)

Power supply: 4.5-5.5V, 2.7-5.5V

Temperature ranges: Commercial (0 to 70

C) and

Industrial (-40 to 85

Packages: PDIL40, PLCC44, VQFP44 1.4, PQFP44

F1, CQPJ44 (window), CDIL40 (window)

Rev. C - 15 January, 2001

TS80C54X2/C58X2

TS87C54X2/C58X2

Table 1. Memory size

PDIL40

PLCC44

PQFP44 F1

VQFP44 1.4

TS80C54X2

TS80C58X2

TS87C54X2

TS87C58X2

ROM (bytes)

EPROM (bytes)

16k

32k

16k

32k

3. Block Diagram

T2EX

(1)

RxD

TxD

Vcc

Vss

(1)

Watch

Dog

(2) (2)

XTAL1

XTAL2

ALE/ PROG

PSEN

CPU

EA/V

(2)

Timer 0

Timer 1

INT

Ctrl

Parallel I/O Ports

Port 0 Port 1 Port 2 Port 3

EUART

RAM

256x8

ROM

/EPROM

16/32Kx8

Timer2

C51

CORE

IB-bus

(2) (2)

RESET

(2) (2)

INT0

INT1

(1): Alternate function of Port 1

(2): Alternate function of Port 3

Rev. C - 15 January, 2001

TS80C54X2/C58X2

TS87C54X2/C58X2

4. SFR Mapping

The Special Function Registers (SFRs) of the TS80C54/58X2 fall into the following categories:

•

C51 core registers: ACC, B, DPH, DPL, PSW, SP, AUXR1

•

I/O port registers: P0, P1, P2, P3

•

Timer registers: T2CON, T2MOD, TCON, TH0, TH1, TH2, TMOD, TL0, TL1, TL2, RCAP2L, RCAP2H

•

Serial I/O port registers: SADDR, SADEN, SBUF, SCON

•

Power and clock control registers: PCON

•

HDW Watchdog Timer Reset: WDTRST, WDTPRG

•

Interrupt system registers: IE, IP, IPH

•

Others: AUXR, CKCON

Table 2. All SFRs with their address and their reset value

Bit

address-

able

0/8

1/9

2/A

3/B

Non Bit addressable

4/C

5/D

6/E

7/F

F8h

F0h

E8h

E0h

D8h

D0h

C8h

C0h

B8h

B0h

A8h

A0h

98h

90h

88h

80h

XX00 0000

1111 1111

0X00 0000

1111 1111

SCON

0000 0000

1111 1111

TCON

0000 0000

1111 1111

0/8

TMOD

0000 0000

0000 0111

1/9

TL0

0000 0000

DPL

0000 0000

2/A

TL1

0000 0000

DPH

0000 0000

3/B

4/C

5/D

6/E

TH0

0000 0000

TH1

0000 0000

AUXR

XXXX XX00

CKCON

XXXX XXX0

PCON

00X1 0000

7/F

SBUF

XXXX XXXX

SADDR

0000 0000

AUXR1

XXXX 0XX0

WDTRST

XXXX XXXX

WDTPRG

XXXX X000

SADEN

0000 0000

IPH

XX00 0000

PSW

0000 0000

T2CON

0000 0000

T2MOD

XXXX XX00

RCAP2L

0000 0000

RCAP2H

0000 0000

TL2

0000 0000

TH2

0000 0000

ACC

0000 0000

FFh

F7h

EFh

E7h

DFh

D7h

CFh

C7h

BFh

B7h

AFh

A7h

9Fh

97h

8Fh

87h

reserved

Rev. C - 15 January, 2001

TS80C54X2/C58X2

TS87C54X2/C58X2

5. Pin Configuration

P1.0 / T2

P1.1 / T2EX

P1.2

P1.3

P1.4

P1.5

P1.6

P1.7

RST

P3.0/RxD

P3.1/TxD

P3.2/INT0

P3.3/INT1

P3.4/T0

P3.5/T1

P3.6/WR

P3.7/RD

XTAL2

XTAL1

VSS

VCC

P0.0 / A0

VSS1/NIC*

P1.1/T2EX

P0.2/AD2

P0.3/AD3

P0.0/AD0

P0.1/AD1

P1.0/T2

P0.1 / A1

P0.2 / A2

P1.4

P1.3

P1.2

P0.3 / A3

P0.4 / A4

P0.5 / A5

P0.6 / A6

P0.7 / A7

EA/VPP

ALE/PROG

PSEN

P2.7 / A15

P2.6 / A14

P2.5 / A13

P2.4 / A12

P2.3 / A11

P2.2 / A10

P2.1 / A9

P2.0 / A8

P1.5

P1.6

P1.7

RST

P3.0/RxD

NIC*

P3.1/TxD

P3.2/INT0

P3.3/INT1

P3.4/T0

P3.5/T1

44 43 42 41 40

P0.4/AD4

P0.5/AD5

P0.6/AD6

P0.7/AD7

EA/VPP

NIC*

ALE/PROG

PSEN

P2.7/A15

P2.6/A14

P2.5/A13

PDIL/

CDIL40

PLCC/CQPJ 44

18 19 20 21 22 23 24 25 26 27 28

P3.6/WR

NIC*

P2.0/A8

XTAL2

XTAL1

P2.2/A10

P2.3/A11

P2.4/A12

P3.7/RD

P2.1/A9

VSS

VSS1/NIC*

P1.1/T2EX

P0.0/AD0

P0.1/AD1

P0.2/AD2

44 43

42 41 40

38 37 36 35 34

P1.5

P1.6

P1.7

RST

P3.0/RxD

NIC*

P3.1/TxD

P3.2/INT0

P3.3/INT1

P3.4/T0

P3.5/T1

P0.4/AD4

P0.5/AD5

P0.6/AD6

P0.7/AD7

EA/VPP

NIC*

ALE/PROG

PSEN

P2.7/A15

P2.6/A14

P2.5/A13

PQFP44 F1

VQFP44 1.4

12 13 14 15 16 17 18 19 20 21 22

XTAL1

NIC*

P2.0/A8

XTAL2

P2.3/A11

P2.4/A12

P2.1/A9

VSS

P2.2/A10

P3.6/WR

P3.7/RD

*NIC: No Internal Connection

P0.3/AD3

P1.0/T2

VCC

P1.4

P1.3

P1.2

VCC

Rev. C - 15 January, 2001

TS80C54X2/C58X2

TS87C54X2/C58X2

Table 3. Pin Description for 40/44 pin packages

MNEMONIC

Vss1

P0.0-P0.7

39-32

PIN NUMBER

DIL

LCC

43-36

VQFP 1.4

37-30

TYPE

I/O

Ground:

0V reference

NAME AND FUNCTION

P1.0-P1.7

1-8

2-9

40-44

1-3

I/O

P2.0-P2.7

21-28

24-31

18-25

I/O

P3.0-P3.7

10-17

11,

13-19

7-13

I/O

Reset

Optional Ground:

Contact the Sales Ofﬁce for ground connection.

Power Supply:

This is the power supply voltage for normal, idle and power-

down operation

Port 0:

Port 0 is an open-drain, bidirectional I/O port. Port 0 pins that have 1s

written to them ﬂoat and can be used as high impedance inputs. Port 0 pins must

be polarized to Vcc or Vss in order to prevent any parasitic current consumption.

Port 0 is also the multiplexed low-order address and data bus during access to

external program and data memory. In this application, it uses strong internal

pull-up when emitting 1s. Port 0 also inputs the code bytes during EPROM

programming. External pull-ups are required during program veriﬁcation during

which P0 outputs the code bytes.

Port 1:

Port 1 is an 8-bit bidirectional I/O port with internal pull-ups. Port 1

pins that have 1s written to them are pulled high by the internal pull-ups and

can be used as inputs. As inputs, Port 1 pins that are externally pulled low will

source current because of the internal pull-ups. Port 1 also receives the low-order

address byte during memory programming and veriﬁcation.

Alternate functions for Port 1 include:

T2 (P1.0):

Timer/Counter 2 external count input/Clockout

T2EX (P1.1):

Timer/Counter 2 Reload/Capture/Direction Control

Port 2:

Port 2 is an 8-bit bidirectional I/O port with internal pull-ups. Port 2

pins that have 1s written to them are pulled high by the internal pull-ups and

can be used as inputs. As inputs, Port 2 pins that are externally pulled low will

source current because of the internal pull-ups. Port 2 emits the high-order address

byte during fetches from external program memory and during accesses to external

data memory that use 16-bit addresses (MOVX @DPTR).In this application, it

uses strong internal pull-ups emitting 1s. During accesses to external data memory

that use 8-bit addresses (MOVX @Ri), port 2 emits the contents of the P2 SFR.

Some Port 2 pins receive the high order address bits during EPROM programming

and veriﬁcation:

P2.0 to P2.5 for A8 to A13

Port 3:

Port 3 is an 8-bit bidirectional I/O port with internal pull-ups. Port 3

pins that have 1s written to them are pulled high by the internal pull-ups and

can be used as inputs. As inputs, Port 3 pins that are externally pulled low will

source current because of the internal pull-ups. Some Port 3 pin P3.4 receive

the high order address bits during EPROM programming and veriﬁcation for

TS8xC58X2 devices.

Port 3 also serves the special features of the 80C51 family, as listed below.

RXD (P3.0):

Serial input port

TXD (P3.1):

Serial output port

INT0 (P3.2):

External interrupt 0

INT1 (P3.3):

External interrupt 1

T0 (P3.4):

Timer 0 external input

T1 (P3.5):

Timer 1 external input

WR (P3.6):

External data memory write strobe

RD (P3.7):

External data memory read strobe

P3.4 also receives A14 during TS87C58X2 EPROM Programming.

Reset:

A high on this pin for two machine cycles while the oscillator is running,

resets the device. An internal diffused resistor to V

permits a power-on reset

using only an external capacitor to V

CC.

Rev. C - 15 January, 2001

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