SC26C94A1A datasheet, PDF - EEWORLD Datasheet

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SC26C94A1A: DescriptionIC 4 CHANNEL(S), 1M bps, SERIAL COMM CONTROLLER, PQCC52, PLASTIC, SOT-238-3, LCC-52, Serial IO/Communication Controller; CategoryThe embedded processor and controller Microcontrollers and processors; File Size211KB，33 Pages; ManufacturerNXP; Websitehttps://www.nxp.com

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SC26C94A1A Overview

IC 4 CHANNEL(S), 1M bps, SERIAL COMM CONTROLLER, PQCC52, PLASTIC, SOT-238-3, LCC-52, Serial IO/Communication Controller

SC26C94A1A Parametric

Parameter Name	Attribute value
Maker	NXP
Parts packaging code	LCC
package instruction	QCCJ, LDCC52,.8SQ
Contacts	52
Reach Compliance Code	compliant
Address bus width	6
boundary scan	NO
maximum clock frequency	8 MHz
letter of agreement	ASYNC, BIT
Data encoding/decoding methods	NRZ
Maximum data transfer rate	0.125 MBps
External data bus width	8
JESD-30 code	S-PQCC-J52
length	19.1262 mm
low power mode	YES
Number of DMA channels
Number of I/O lines	16
Number of serial I/Os	4
Number of terminals	52
On-chip data RAM width
Maximum operating temperature	85 °C
Minimum operating temperature	-40 °C
Package body material	PLASTIC/EPOXY
encapsulated code	QCCJ
Encapsulate equivalent code	LDCC52,.8SQ
Package shape	SQUARE
Package form	CHIP CARRIER
power supply	5 V
Certification status	Not Qualified
RAM (number of words)	0
Maximum seat height	4.57 mm
Maximum slew rate	50 mA
Maximum supply voltage	5.5 V
Minimum supply voltage	4.5 V
Nominal supply voltage	5 V
surface mount	YES
technology	CMOS
Temperature level	INDUSTRIAL
Terminal form	J BEND
Terminal pitch	1.27 mm
Terminal location	QUAD
width	19.1262 mm
uPs/uCs/peripheral integrated circuit type	SERIAL IO/COMMUNICATION CONTROLLER, SERIAL

SC26C94A1A Preview

Philips Semiconductors

Product specification

Quad universal asynchronous receiver/transmitter (QUART)

SC26C94

DESCRIPTION

The 26C94 quad universal asynchronous receiver/transmitter

(QUART) combines four enhanced Philips Semiconductors

industry-standard UARTs with an innovative interrupt scheme that

can vastly minimize host processor overhead. It is implemented

using Philips Semiconductors’ high-speed CMOS process that

combines small die size and cost with low power consumption.

The operating speed of each receiver and transmitter can be

selected independently at one of eighteen fixed baud rates, a 16X

clock derived from a programmable counter/timer, or an external 1X

or 16X clock. The baud rate generator and counter/timer can

operate directly from a crystal or from external clock inputs. The

ability to independently program the operating speed of the receiver

and transmitter make the QUART particularly attractive for

dual-speed channel applications such as clustered terminal

systems.

Each receiver is buffered with eight character FIFOs (first-in-first-out

memories) and one shift register to minimize the potential for

receiver overrun and to reduce interrupt overhead in interrupt driven

systems. In addition, a handshaking capability is provided to disable

a remote UART transmitter when the receiver buffer is full. (RTS

control)

The 2694 provides a power-down mode in which the oscillator is

stopped and the register contents are stored. This results in reduced

power consumption on the order of several magnitudes. The

QUART is fully TTL compatible and operates from a single +5V

power supply.

PIN CONFIGURATIONS

A5:0

CEN

RDN

WRN

D7-0

DACKN

IACKN

RQN

RESET

X1/CLK

RDa-d

I/O0a–d

I/O1a–d

I/O2a–d

I/O3a–d

TDa-d

SD00158

•

Programmable channel mode

•

Programmable interrupt priorities

•

Identification of highest priority interrupt

•

Global interrupt register set provides data from interrupting

channel

–

Normal (full-duplex), automatic echo, local loop back, remote

loopback

FEATURES

•

New low overhead interrupt control

•

Four Philips Semiconductors industry-standard UARTs

•

Eight byte receive FIFO and eight byte transmit FIFO for each

UART

•

Programmable data format:

–

5 to 8 data bits plus parity

–

Odd, even, no parity or force parity

–

1, 1.5 or 2 stop bits programmable in 1/16-bit increments

•

Baud rate for the receiver and transmitter selectable from:

–

23 fixed rates: 50 to 230.4K baud Non-standard rates to 1.0M

baud

–

User-defined rates from the programmable counter/timer

associated with each of two blocks

–

External 1x or 16x clock

•

Parity, framing, and overrun error detection

•

False start bit detection

•

Line break detection and generation

ORDERING INFORMATION

PACKAGES

48-Pin Plastic Dual In-Line Package (DIP)

52-Pin Plastic Leaded Chip Carrier (PLCC) Package

•

Vectored interrupts with programmable vector format

•

IACKN and DTACKN signals

•

Built-in baud rate generator with choice of 18 rates

•

Four I/O pins per UART for modem controls, clocks, etc.

•

Power down mode

•

High-speed CMOS technology

•

52-pin PLCC and 48-pin DIP

•

Commercial and industrial temperature ranges available

•

On-chip crystal oscillator

•

TTL compatible

•

Single +5V power supply with low power mode

•

Two multifunction programmable 16-bit counter/timers

•

1MHz 16x mode operation

•

30ns data bus release time

•

“Watch Dog” timer for each receiver

COMMERCIAL

= +5V +10%,

= 0

C to +70

SC26C94C1N

SC26C94C1A

INDUSTRIAL

= +5V +10%,

= –40

C to +85

SC26C94A1N

SC26C94A1A

DWG #

SOT240-1

SOT238-3

1995 May 1

853-1471 15179

Philips Semiconductors

Product specification

Quad universal asynchronous receiver/transmitter (QUART)

SC26C94

PIN CONFIGURATIONS

48-Pin Dual-In-Line Package

X1/CLK

TXDD

RXDD

IRQN

47 V

DACKN

IACKN

TXDB

RESET

TXDC

RXDC

I/O2D

I/O1D

I/O0D

I/O2C

I/O1C

I/O0C

RXDB

52-Pin PLCC Package

RDN

CEN

V SS

VCC

WRN

46 A5

45 IRQN

44 RXDD

43 TXDD

42 X1/CLK

41 X2

40 V

39 I/O3D

38 RESET

37 TXDC

36 RXDC

35 I/O2D

34 I/O1D

D6 10

D5 11

D4 12

D3 13

D2 15

I/O3B 16

D1 17

D0 18

RXDA 19

TXDA 20

I/O2B

I/O1B

I/O0B

I/O3A

I/O2A

I/O1A

I/O0A

V SS

I/O0C

I/O1C

31 32

I/O2C

I/O3C

I/O0D

A0 10

WRN 11

CEN 14

RDN 15

DACKN 16

IACKN 17

TXDB 18

RXDB 19

D7 20

D6 21

D5 22

D4 23

D3 24

37 V

I/O0A

I/O1A

I/O2A

I/O0B

I/O1B

I/O2B

TXDA

RXDA

25 V

SD00159

ABSOLUTE MAXIMUM RATINGS

1, 2

SYMBOL

STG

PARAMETER

Operating ambient temperature range

Storage temperature range

Voltage from V

to GND

Voltage from any pin to ground

Power dissipation

RATING

Note 4

–65 to +150

–0.5 to +7.0

–0.5 to V

+0.5

UNIT

NOTES:

1. Stresses above those listed under Absolute Maximum Ratings may cause permanent damage to the device. This is a stress rating only and

functional operation of the device at these or any other condition above those indicated in the operation section of this specification is not

implied.

2. For operating at elevated temperatures, the device must be derated based on +150°C maximum junction temperature.

3. This product includes circuitry specifically designed for the protection of its internal devices from damaging effects of excessive static

charge. Nonetheless, it is suggested that conventional precautions be taken to avoid applying any voltages larger than the rated maxima.

4. Parameters are valid over specified temperature range. See ordering information table for applicable temperature range and operating

supply range.

1995 May 1

Philips Semiconductors

Product specification

Quad universal asynchronous receiver/transmitter (QUART)

SC26C94

BLOCK DIAGRAM

INTERNAL DATA

BUS

D0–D7

BUS BUFFER

CHANNEL A

8 BYTE TRANSMIT

FIFO

TxDA

TRANSMIT SHIFT

8 BYTE

RECEIVE FIFO

RxDA

RECEIVE SHIFT

MR 0, 1, 2

CSR Rx

CSR Tx

X1/CLK

TIMING

CRYSTAL

OSCILLATOR

POWER UP-DOWN

LOGIC

BAUD RATE

GENERATOR

CHANNEL B

(AS ABOVE)

INPUT PORT

CHANGE-OF-

STATE

DETECTORS (4)

IPCR

ACR

TxDB

RxDB

DUART

COMMON

DUART AB

TIMING

CONTROL

RDN

WRN

CEN

A0–A5

RESET

DACKN

OPERATION CONTROL

ADDRESS

DECODE

R/W CONTROL

DUART CD

TXDC

TXDD

RXDC

RXDD

SAME AS

DUART AB

OUTPUT PORT

FUNCTION SELECT

LOGIC

OPCR

TIMING

CLOCK

SELECTORS

COUNTER/

TIMER

ACR

CTUR

CTLR

1:0

I/O[3:0]B

I/O[3:0]A

I/O[3:0]C

I/O[3:0]D

INTERRUPT ARBITRATION

IACKN

IRQN

•V

SS1

•V

SS2

•V

SS3

•V

SS4

LOGIC

GLOBAL

REGISTERS

INTERRUPT CONTROL

IMR

ISR

SD00160

1995 May 1

Philips Semiconductors

Product specification

Quad universal asynchronous receiver/transmitter (QUART)

SC26C94

PIN DESCRIPTION

MNEMONIC

CEN

A5:0

D7:0

RDN

WRN

DACKN

TYPE

I/O

NAME AND FUNCTION

Chip Select:

Active low input that, in conjunction with RDN or WRN, indicates that the host MPU is trying to

access a QUART register. CEN must be inactive when IACKN is asserted.

Address Lines:

These inputs select a 26C94 register to be read or written by the host MPU.

8-bit Bidirectional Data Bus:

Used by the host MPU to read and write 26C94 registers.

Read Strobe:

Active low input. When this line is asserted simultaneously with CEN, the 26C94 places the

contents of the register selected by A5:0 on the D7:0 lines.

Write Strobe:

Active low input. When this line is asserted simultaneously with CEN, the 26C94 writes the data

on D7:0 into the register selected by A5:0.

Data ACKnowledge:

Active low, open-drain output to the host MPU, which is asserted subsequent to a read or

write operation. For a read operation, assertion of DACKN indicates that register data is valid on D7:0. For a

write operation, it indicates that the data on D7:0 has been captured into the indicated register. This signal

corresponds to READYN on 80x86 processors and DTACKN on 680x0 processors.

Interrupt Request:

This active low open-drain output to the host MPU indicating that one or more of the

enabled UART interrupt sources has reached an interrupt value which exceeds that pre-programmed by host

software. The IRQN can be used directly as a 680x0 processor input; it must be inverted for use as an 80x86

interrupt input. This signal requires an external pull-up resistor.

Interrupt ACKnowledge:

Active low input indicates host MPU is acknowledging an interrupt requested. The

26C94 responds by placing an interrupt vector or interrupt vector modified on D7-D0 and asserting DACKN. This

signal updates the CIR register in the interrupt logic. CEN must be high during this cycle.

Transmit Data:

Serial outputs from the four UARTs.

Receive Data:

Serial inputs to the four UARTs/

Input/Output 0:

A multi-use input or output signal for each UART. These pins can be used as general purpose

inputs, Clear to Send inputs, 1X or 16X Transmit Clock outputs or general purpose outputs. Change-of-state

detection is provided for these pins.

Input/Output 1:

A multi-use input or output signal for each UART. These pins can be used as general purpose

or 1X or 16X transmit clock inputs, or general purpose 1X or 16X receive clock outputs. Change-of-state

detection is provided for these pins. In addition, I/O1a and I/O1c can be used as Counter/Timer inputs and I/O1b

and I/O1d can be used as Counter/Timer outputs.

Input/Output 2:

A multi-use input or output signal for each UART. These pins can be used as general purpose

inputs, 1X or 16X receive clock inputs, general purpose outputs, RTS output or 1X or 16X receive clock outputs.

Input/Output 3:

A multi-use input or output signal for each UART. These pins can be used as general purpose

inputs, 1X or 16X transmit clock inputs, general purpose outputs, or 1X or 16X transmit clock outputs.

Master Reset:

Active high reset for the 26C94 logic. Must be asserted at power-up, may be asserted at other

times that the system is to be reset and restarted. OSC set to divide by 1, MR pointer set to 1, DACKN enabled,

I/O pins to input. Registers reset: OPR, CIR. IRQN, DTACKN, IVR Interrupt Vector, Power Down, Test registers,

FIFO pointers, Baud rate generator, Error Status, Watch Dog Timers, Change of State detectors, counter/timer to

timer, Transmitter and Receiver controllers and all interrupt bits. If reset pin is not used, then first chip access

should be to celar ‘power-down’ mode.

Crystal 1 or Communication Clock:

This pin is normally connected to one side of a 3.6864MHz or a

7.3728MHz crystal, or can be connected to an external clock up to 8MHz.

Crystal 2:

If a crystal is used, this pin should be connected to its other terminal. If an external clock is applied to

X1, this pin should be left unconnected.

Power and grounds:

respectively.

BLOCK A

BUS

INTERFACE

A0-A5

D (7:0)

INTERRUPT CONTROL

DTACKN

IACKN

BLOCK B

UARTS C/D

I/O CONTROL

I/O PORT CONTROL

COUNTER/TIMER

I/O PORT CONTROL

UARTS A/B

BAUD

RATE

GENERATOR

IRQN

IACKN

TDa-d

RDa-d

I/O0a-d

I/O

I/O1a-d

I/O

I/O2a-d

I/O3a-d

RESET

I/O

X1/CLK

, V

SD00161

Figure 1. Channel Architecture

1995 May 1

Philips Semiconductors

Product specification

Quad universal asynchronous receiver/transmitter (QUART)

SC26C94

Table 1.

QUART Registers

READ (RDN = Low)

Mode Register a (MR0a, MR1a, MR2a)

Status Register a (SRa)

Reserved

Receive Holding Register a (RxFIFOa)

Input Port Change Reg ab (IPCRab)

Interrupt Status Reg ab (ISRab)

Counter/Timer Upper ab (CTUab)

Counter/Timer Lower ab (CTLab)

Mode Register b (MR0b, MR1b, MR2b)

Status Register b (SRb)

Reserved

Receive Holding Register b (RxFIFOb)

Output Port Register ab (OPRab)

Input Port Register ab (IPRab)

Start Counter ab

Stop Counter ab

Mode Register c (MR0c, MR1c, MR2c)

Status Register c (SRc)

Reserved

Receive Holding Register c (RxFIFOc)

Input Port Change Reg cd (IPCRcd)

Interrupt Status Reg cd (ISRcd)

Counter/Timer Upper cd (CTUcd)

Counter/Timer Lower cd (CTLcd)

Mode Register d (MR0d, MR1d, MR2d)

Status Register d (SRd)

Reserved

Receive Holding Register d (RxFIFOd)

Output Port Register cd (OPRcd)

Input Port Register cd (IPRcd)

Start Counter cd

Stop Counter cd

Bidding Control Register a (BCRa)

Bidding Control Register b (BCRb)

Bidding Control Register c (BCRc)

Bidding Control Register d (BCRd)

Reserved

Current Interrupt Register (CIR)

Global Interrupting Channel Reg (GICR)

Global Int Byte Count Reg (GIBCR)

Global Receive Holding Reg (GRxFIFO)

Interrupt Control Register (ICR)

Reserved

Test Mode

Reserved

WRITE (WRN = Low)

Mode Register a (MR0a, MR1a, MR2a)

Clock Select Register a (CSRa)

Command Register a (CRa)

Transmit Holding Register a (TxFIFOa)

Auxiliary Control Reg ab (ACRab)

Interrupt Mask Reg ab (IMRab)

Counter/Timer Upper Reg ab (CTURab)

Counter/Timer Lower Reg ab (CTLRab)

Mode Register b (MR0b, MR1b, MR2b)

Clock Select Register b (CSRb)

Command Register b (CRb)

Transmit Holding Register b (TxFIFOb)

Output Port Register ab (OPRab)

I/OPCRa (I/O Port Control Reg a)

I/OPCRb (I/O Port Control Reg b)

Reserved

Mode Register c (MR0c, MR1c, MR2c)

Clock Select Register c (CSRc)

Command Register c (CRc)

Transmit Holding Register c (TxFIFOc)

Auxiliary Control Reg cd (ACRcd)

Interrupt Mask Reg cd (IMRcd)

Counter/Timer Upper Reg cd (CTURcd)

Counter/Timer Lower Reg cd (CTLRcd)

Mode Register d (MR0d, MR1d, MR2d)

Clock Select Register d (CSRd)

Command Register d (CRd)

Transmit Holding Register d (TxFIFOd)

Output Port Register cd (OPRcd)

I/OPCRc (I/O Port Control Reg c)

I/OPCRd (I/O Port Control Reg d)

Reserved

Bidding Control Register a (BCRa)

Bidding Control Register b (BCRb)

Bidding Control Register c (BCRc)

Bidding Control Register d (BCRd)

Power Down

Power Up

Disable DACKN

Enable DACKN

Reserved

Interrupt Vector Register (IVR)

Update CIR

Global Transmit Holding Reg (GTxFIFO)

Interrupt Control Register (ICR)

BRG Rate. 00 = low; 01 = high

Set X1/CLK divide by two

Set X1/CLK Normal

Reserved

Test Mode

Reserved

A5:0

000000

000001

000010

000011

000100

000101

000110

000111

001000

001001

001010

001011

001100

001101

001110

001111

010000

010001

010010

010011

010100

010101

010110

010111

011000

011001

011010

011011

011100

011101

011110

011111

100000

100001

100010

100011

100100

100101

100110

100111

101000

101001

101010

101011

101100

101101

101110

101111

110000–111000

111001

111010–111111

1995 May 1

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SC26C94A1A Related Products

	SC26C94A1A	SC26C94C1A	SC26C94A1N	SC26C94C1N	SC26C94A1A-T	SC26C94C1A-T
Description	IC 4 CHANNEL(S), 1M bps, SERIAL COMM CONTROLLER, PQCC52, PLASTIC, SOT-238-3, LCC-52, Serial IO/Communication Controller	IC 4 CHANNEL(S), 1M bps, SERIAL COMM CONTROLLER, PQCC52, PLASTIC, SOT-238-3, LCC-52, Serial IO/Communication Controller	IC 4 CHANNEL(S), 1M bps, SERIAL COMM CONTROLLER, PDIP48, PLASTIC, DIP-48, Serial IO/Communication Controller	IC 4 CHANNEL(S), 1M bps, SERIAL COMM CONTROLLER, PDIP48, PLASTIC, DIP-48, Serial IO/Communication Controller	IC 4 CHANNEL(S), 1M bps, SERIAL COMM CONTROLLER, PQCC52, Serial IO/Communication Controller	IC 4 CHANNEL(S), 1M bps, SERIAL COMM CONTROLLER, PQCC52, Serial IO/Communication Controller
Maker	NXP	NXP	NXP	NXP	NXP	NXP
package instruction	QCCJ, LDCC52,.8SQ	QCCJ, LDCC52,.8SQ	DIP, DIP48,.6	DIP, DIP48,.6	QCCJ,	QCCJ,
Reach Compliance Code	compliant	unknown	compliant	compliant	unknown	unknown
Address bus width	6	6	6	6	6	6
boundary scan	NO	NO	NO	NO	NO	NO
maximum clock frequency	8 MHz	8 MHz	8 MHz	8 MHz	8 MHz	8 MHz
letter of agreement	ASYNC, BIT	ASYNC, BIT	ASYNC, BIT	ASYNC, BIT	ASYNC, BIT	ASYNC, BIT
Data encoding/decoding methods	NRZ	NRZ	NRZ	NRZ	NRZ	NRZ
Maximum data transfer rate	0.125 MBps	0.125 MBps	0.125 MBps	0.125 MBps	0.125 MBps	0.125 MBps
External data bus width	8	8	8	8	8	8
JESD-30 code	S-PQCC-J52	S-PQCC-J52	R-PDIP-T48	R-PDIP-T48	S-PQCC-J52	S-PQCC-J52
length	19.1262 mm	19.1262 mm	62.1 mm	62.1 mm	19.1262 mm	19.1262 mm
low power mode	YES	YES	YES	YES	YES	YES
Number of I/O lines	16	16	16	16	16	16
Number of serial I/Os	4	4	4	4	4	4
Number of terminals	52	52	48	48	52	52
Maximum operating temperature	85 °C	70 °C	85 °C	70 °C	85 °C	70 °C
Package body material	PLASTIC/EPOXY	PLASTIC/EPOXY	PLASTIC/EPOXY	PLASTIC/EPOXY	PLASTIC/EPOXY	PLASTIC/EPOXY
encapsulated code	QCCJ	QCCJ	DIP	DIP	QCCJ	QCCJ
Package shape	SQUARE	SQUARE	RECTANGULAR	RECTANGULAR	SQUARE	SQUARE
Package form	CHIP CARRIER	CHIP CARRIER	IN-LINE	IN-LINE	CHIP CARRIER	CHIP CARRIER
Certification status	Not Qualified	Not Qualified	Not Qualified	Not Qualified	Not Qualified	Not Qualified
Maximum seat height	4.57 mm	4.57 mm	4.9 mm	4.9 mm	4.57 mm	4.57 mm
Maximum slew rate	50 mA	50 mA	50 mA	50 mA	50 mA	50 mA
Maximum supply voltage	5.5 V	5.5 V	5.5 V	5.5 V	5.5 V	5.5 V
Minimum supply voltage	4.5 V	4.5 V	4.5 V	4.5 V	4.5 V	4.5 V
Nominal supply voltage	5 V	5 V	5 V	5 V	5 V	5 V
surface mount	YES	YES	NO	NO	YES	YES
technology	CMOS	CMOS	CMOS	CMOS	CMOS	CMOS
Temperature level	INDUSTRIAL	COMMERCIAL	INDUSTRIAL	COMMERCIAL	INDUSTRIAL	COMMERCIAL
Terminal form	J BEND	J BEND	THROUGH-HOLE	THROUGH-HOLE	J BEND	J BEND
Terminal pitch	1.27 mm	1.27 mm	2.54 mm	2.54 mm	1.27 mm	1.27 mm
Terminal location	QUAD	QUAD	DUAL	DUAL	QUAD	QUAD
width	19.1262 mm	19.1262 mm	15.24 mm	15.24 mm	19.1262 mm	19.1262 mm
uPs/uCs/peripheral integrated circuit type	SERIAL IO/COMMUNICATION CONTROLLER, SERIAL	SERIAL IO/COMMUNICATION CONTROLLER, SERIAL	SERIAL IO/COMMUNICATION CONTROLLER, SERIAL	SERIAL IO/COMMUNICATION CONTROLLER, SERIAL	SERIAL IO/COMMUNICATION CONTROLLER, SERIAL	SERIAL IO/COMMUNICATION CONTROLLER, SERIAL
Parts packaging code	LCC	LCC	DIP	DIP	-	-
Contacts	52	52	48	48	-	-
Encapsulate equivalent code	LDCC52,.8SQ	LDCC52,.8SQ	DIP48,.6	DIP48,.6	-	-
power supply	5 V	5 V	5 V	5 V	-	-

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