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ICS552G-02

Description
Low Skew Clock Driver, 552 Series, 8 True Output(s), 0 Inverted Output(s), CMOS, PDSO16, 0.173 INCH, TSSOP-16
Categorylogic    logic   
File Size35KB，6 Pages
ManufacturerIDT (Integrated Device Technology)
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ICS552G-02 Overview

Low Skew Clock Driver, 552 Series, 8 True Output(s), 0 Inverted Output(s), CMOS, PDSO16, 0.173 INCH, TSSOP-16

ICS552G-02 Parametric

Parameter NameAttribute value
Is it lead-free?Contains lead
Is it Rohs certified?incompatible
MakerIDT (Integrated Device Technology)
Parts packaging codeTSSOP
package instructionTSSOP,
Contacts16
Reach Compliance Codenot_compliant
series552
Input adjustmentMUX
JESD-30 codeR-PDSO-G16
JESD-609 codee0
length5 mm
Logic integrated circuit typeLOW SKEW CLOCK DRIVER
Humidity sensitivity level1
Number of functions1
Number of inverted outputs
Number of terminals16
Actual output times8
Maximum operating temperature70 °C
Minimum operating temperature
Output characteristics3-STATE
Package body materialPLASTIC/EPOXY
encapsulated codeTSSOP
Package shapeRECTANGULAR
Package formSMALL OUTLINE, THIN PROFILE, SHRINK PITCH
Peak Reflow Temperature (Celsius)240
Certification statusNot Qualified
Same Edge Skew-Max（tskwd）0.05 ns
Maximum seat height1.2 mm
Maximum supply voltage (Vsup)5.25 V
Minimum supply voltage (Vsup)2.375 V
Nominal supply voltage (Vsup)2.5 V
surface mountYES
technologyCMOS
Temperature levelCOMMERCIAL
Terminal surfaceTin/Lead (Sn/Pb)
Terminal formGULL WING
Terminal pitch0.65 mm
Terminal locationDUAL
Maximum time at peak reflow temperature20
width4.4 mm
minfmax200 MHz

ICS552G-02 Preview

ICS552-02
L
OW
S
KEW
2 I
NPUT
MUX
AND
1
TO
8 C
LOCK
B
UFFER
Description
The ICS552-02 is a low skew, single-input to eight-
output clock buffer. It is part of ICS’ Clock Blocks
TM
family. See the ICS553 for a 1 to 4 low skew buffer. For
more than 8 outputs see the MK74CBxxx Buffalo
TM
series of clock drivers.
ICS makes many non-PLL and PLL based low skew
output devices as well as Zero Delay Buffers to
synchronize clocks. Contact us for all of your clocking
needs.
Features
•
•
•
•
•
•
•
•
Extremely low skew outputs (50ps maximum)
Packaged in 16 pin TSSOP
Low power CMOS technology
Operating Voltages of 2.5 V to 5 V
Output Enable pin tri-states outputs
5 V tolerant input clocks
Input/Output clock frequency up to 200 MHz
Input clock multiplexer simplifies clock selection
Block Diagram
Q0
Q1
Q2
IN A
1
Q3
Q4
Q5
Q6
Q7
IN B
0
S E LA
OE
MDS 552-02 B
In tegr ated C ir cu it S yst ems
q
1
5 25 Ra ce Str eet, San Jose, C A 95 126
q
Revision 050401
tel ( 408) 2 95-9 800
q
www. i c s t. c om
P R E L I M I N A RY I N FO R M ATI O N
ICS552-02
L
OW
S
KEW
2 I
NPUT
MUX
AND
1
TO
8 C
LOCK
Pin Assignment
OE
VDD
Q0
Q1
Q2
Q3
GND
INB
1
2
3
4
5
6
7
8
16
15
14
13
12
11
10
9
SELA
VDD
Q7
Q6
Q5
Q4
GND
INA
Input Source Select
SELA
0
1
Input
INB
INA
16 Pin TSSOP
Pin Descriptions
Pin
Number
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
Pin
Name
OE
VDD
Q0
Q1
Q2
Q3
GND
INB
INA
GND
Q4
Q5
Q6
Q7
VDD
SELA
Pin
Type
Input
Power
Output
Output
Output
Output
Power
Input
Input
Power
Output
Output
Output
Output
Power
Input
Pin Description
Output Enable. Tri-states outputs when low. Internal pull-up resistor.
Connect to +2.5V, +3.3V or +5.0V. Must be the same as pin 15.
Clock Output 0
Clock Output 1
Clock Output 2
Clock Output 3
Connect to ground.
Clock Input B. 5V tolerant input.
Clock Input A. 5V tolerant input.
Connect to ground.
Clock Output 4
Clock Output 5
Clock Output 6
Clock Output 7
Connect to + 2.5V, +3.3V or +5.0V. Must be the same as pin 2.
Selects either INA or INB. Internal pull-up resistor.
External Components
A minimum number of external components are required for proper operation. Decoupling capacitors of
0.01
µF
should be connected between VDD on pin 2 and GND on pin 7, and between VDD on pin 15 and
GND on pin 10, as close to the device as possible. A 33
Ω
series terminating resistor should be used on
each clock output if the trace is longer than 1 inch.
To achieve the low output skews that the ICS552-02 is capable of, careful attention must be paid to board
layout. Essentially, all 8 outputs must have identical terminations, identical loads, and identical trace
geometries. If they do not, the output skew will be degraded. For example, using a 30
Ω
series termination
on one output (with 33Ω on the others) will cause at least 15ps of skew.
MDS 552-02 B
Int egrat ed C ircuit Syste ms
q
2
525 R ace S tr eet, San Jose, CA 95126
q
Revision 050401
t el (40 8) 295 -9800
q
w ww. ic s t .c o m
P R E L I M I N A RY I N FO R M ATI O N
ICS552-02
L
OW
S
KEW
2 I
NPUT
MUX
AND
1
TO
8 C
LOCK
Absolute Maximum Ratings
Stresses above the ratings listed below can cause permanent damage to the ICS552-02. These ratings,
which are standard values for ICS commercially rated parts, are stress ratings only. Functional operation of
the device at these or any other conditions above those indicated in the operational sections of the
specifications is not implied. Exposure to absolute maximum rating conditions for extended periods can
affect product reliability. Electrical parameters are guaranteed only over the recommended operating
temperature range.
Item
Supply Voltage, VDD
All Inputs and Outputs
Ambient Operating Temperature
Storage Temperature
Junction Temperature
Soldering Temperature
7V
Rating
-0.5 V to VDD+0.5 V
0 to +70
°C
-65 to +150
°C
175
°C
260
°C
Recommended Operation Conditions
Parameter
Ambient Operating Temperature
Power Supply Voltage (measured in respect to GND)
Min.
0
+2.375
Typ.
–
Max.
+70
+5.25
Units
°C
V
DC Electrical Characteristics
VDD=2.5 V ±5%
, Ambient temperature 0 to +70°C, unless stated otherwise
Parameter
Operating Voltage
Input High Voltage, INA, INB
Input Low Voltage, INA, INB
Input High Voltage, OE, SELA
Input Low Voltage, OE, SELA
Output High Voltage
Output Low Voltage
Operating Supply Current
Short Circuit Current
Symbol
VDD
V
IH
V
IL
V
IH
V
IL
V
OH
V
OL
IDD
I
OS
Conditions
Note 1
Note 1
Min.
2.375
VDD/2+0.5
2
Typ.
Max.
2.625
5.5
VDD/2-0.5
VDD
0.4
Units
V
V
V
V
V
V
V
mA
mA
I
OH
= -16 mA
I
OL
= 16 mA
No load, 135 MHz
Each output
2
0.5
35
60
MDS 552-02 B
Int egrat ed C ircuit Syste ms
q
3
525 R ace S tr eet, San Jose, CA 95126
q
Revision 050401
t el (40 8) 295 -9800
q
w ww. ic s t .c o m
P R E L I M I N A RY I N FO R M ATI O N
ICS552-02
L
OW
S
KEW
2 I
NPUT
MUX
AND
1
TO
8 C
LOCK
DC Electrical Characteristics (continued)
VDD=3.3 V ±5%
, Ambient temperature 0 to +70°C, unless stated otherwise
Parameter
Operating Voltage
Input High Voltage, INA, INB
Input Low Voltage, INA, INB
Input High Voltage, OE, SELA
Input Low Voltage, OE, SELA
Output High Voltage
Output Low Voltage
Output High Voltage (CMOS
Level)
Operating Supply Current
Short Circuit Current
Symbol
VDD
V
IH
V
IL
V
IH
V
IL
V
OH
V
OL
V
OH
IDD
I
OS
Conditions
Note 1
Note 1
Min.
3.135
VDD/2+0.7
2
Typ.
Max.
3.465
5.5
VDD/2-0.7
VDD
0.4
Units
V
V
V
V
V
V
V
V
I
OH
= -25 mA
I
OH
= 25 mA
I
OH
= -12 mA
No load, 135 MHz
Each output
2.4
0.8
VDD-0.4
50
80
mA
mA
VDD=5 V ±5%
, Ambient temperature 0 to +70°C, unless stated otherwise
Parameter
Operating Voltage
Input High Voltage, INA, INB
Input Low Voltage, INA, INB
Input High Voltage, OE, SELA
Input Low Voltage, OE, SELA
Output High Voltage
Output Low Voltage
Output High Voltage (CMOS
Level)
Operating Supply Current
Short Circuit Current
Symbol
VDD
V
IH
V
IL
V
IH
V
IL
V
OH
V
OL
V
OH
IDD
I
OS
Conditions
Note 1
Note 1
Min.
4.75
VDD/2+1
2
Typ.
Max.
5.25
5.5
VDD/2-1
VDD
0.4
Units
V
V
V
V
V
V
V
V
I
OH
= -45 mA
I
OL
= 45 mA
I
OH
= -12 mA
No load, 135 MHz
Each output
2.4
0.8
VDD-0.4
85
100
mA
mA
Note: 1. Nominal switching threshold is VDD/2
MDS 552-02 B
Int egrat ed C ircuit Syste ms
q
4
525 R ace S tr eet, San Jose, CA 95126
q
Revision 050401
t el (40 8) 295 -9800
q
w ww. ic s t .c o m
P R E L I M I N A RY I N FO R M ATI O N
ICS552-02
L
OW
S
KEW
2 I
NPUT
MUX
AND
1
TO
8 C
LOCK
AC Electrical Characteristics
VDD = 2.5V ±5%
, Ambient Temperature 0 to +70° C, unless stated otherwise
Parameter
Input Frequency
Output Rise Time
Output Fall Time
Propagation Delay
Output to output skew
Input A to Input B skew
t
OR
t
OF
Note 1
Note 2
Note 3
Rising edges at VDD/2
0.8 to 2.0 V, C
L
=15 pF
2.0 to 0.8 V, C
L
=15 pF
Symbol
Conditions
Min.
0
Typ.
1.5
1.5
3.5
0
0
Max. Units
200
MHz
ns
ns
ns
50
50
ps
ps
VDD = 3.3V ±5%
, Ambient Temperature 0 to +70° C, unless stated otherwise
Parameter
Input Frequency
Output Rise Time
Output Fall Time
Propagation Delay
Output to output skew
Input A to Input B skew
t
OR
t
OF
Note 1
Note 2
Note 3
Rising edges at VDD/2
0.8 to 2.0 V, C
L
=15 pF
2.0 to 0.8 V, C
L
=15 pF
Symbol
Conditions
Min.
0
Typ.
1.0
1.0
3.0
0
0
Max. Units
200
MHz
ns
ns
ns
50
50
ps
ps
VDD = 5.0V ±5%
, Ambient Temperature 0 to +70° C, unless stated otherwise
Parameter
Input Frequency
Output Rise Time
Output Fall Time
Propagation Delay
Output to output skew
Input A to Input B skew
t
OR
t
OF
Note 1
Note 2
Note 3
Rising edges at VDD/2
0.8 to 2.0 V, C
L
=15 pF
2.0 to 0.8 V, C
L
=15 pF
Symbol
Conditions
Min.
0
Typ.
0.7
0.7
2.8
0
0
Max. Units
200
MHz
ns
ns
ns
50
50
ps
ps
Notes: 1. With rail-to-rail input clock.
2. Between any two outputs with equal loading.
3. Propagation delay matching through the part.
4. Duty cycle on outputs will match incoming clock duty cycle. Consult ICS for tight duty cycle clock
generators.
MDS 552-02 B
Int egrat ed C ircuit Syste ms
q
5
525 R ace S tr eet, San Jose, CA 95126
q
Revision 050401
t el (40 8) 295 -9800
q
w ww. ic s t .c o m
More (Only the first 5 pages are displayed. Please Download Datasheet to view the full content.) >

ICS552G-02 Related Products

ICS552G-02 ICS552G-02T
Description Low Skew Clock Driver, 552 Series, 8 True Output(s), 0 Inverted Output(s), CMOS, PDSO16, 0.173 INCH, TSSOP-16 Low Skew Clock Driver, 552 Series, 8 True Output(s), 0 Inverted Output(s), CMOS, PDSO16, 0.173 INCH, TSSOP-16
Maker IDT (Integrated Device Technology) IDT (Integrated Device Technology)
Parts packaging code TSSOP TSSOP
package instruction TSSOP, TSSOP,
Contacts 16 16
Reach Compliance Code not_compliant unknown
series 552 552
Input adjustment MUX MUX
JESD-30 code R-PDSO-G16 R-PDSO-G16
length 5 mm 5 mm
Logic integrated circuit type LOW SKEW CLOCK DRIVER LOW SKEW CLOCK DRIVER
Number of functions 1 1
Number of terminals 16 16
Actual output times 8 8
Maximum operating temperature 70 °C 70 °C
Output characteristics 3-STATE 3-STATE
Package body material PLASTIC/EPOXY PLASTIC/EPOXY
encapsulated code TSSOP TSSOP
Package shape RECTANGULAR RECTANGULAR
Package form SMALL OUTLINE, THIN PROFILE, SHRINK PITCH SMALL OUTLINE, THIN PROFILE, SHRINK PITCH
Certification status Not Qualified Not Qualified
Same Edge Skew-Max（tskwd） 0.05 ns 0.05 ns
Maximum seat height 1.2 mm 1.2 mm
Maximum supply voltage (Vsup) 5.25 V 5.25 V
Minimum supply voltage (Vsup) 2.375 V 2.375 V
Nominal supply voltage (Vsup) 2.5 V 2.5 V
surface mount YES YES
technology CMOS CMOS
Temperature level COMMERCIAL COMMERCIAL
Terminal form GULL WING GULL WING
Terminal pitch 0.65 mm 0.65 mm
Terminal location DUAL DUAL
width 4.4 mm 4.4 mm
minfmax 200 MHz 200 MHz

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